Jitter Reduction in SONET Clock Recovery via Phase Compensation
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Solution Overview
Problem
Existing methods for mapping asynchronous subscriber traffic onto SONET/SDH frames introduce waiting time jitter, particularly when frequency ratios between tributary and local clocks vary, leading to timing errors and signal degradation in critical applications like HDTV or SONET over SONET scenarios.
Innovation Solution
A method to minimize jitter by measuring and compensating phase differences between data and local clocks, using a timing reference that accounts for ambiguity and noise, implemented through phase error non-linearity, notch filtering, or error estimation techniques to suppress low-level fluctuations and maintain accurate phase estimation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If stuff bytes are inserted and stripped from SPE tributaries to compensate rate differences, then the FIFO-fill signals can adapt to frequency variations, but waiting time jitter is introduced in the recovered subscriber signal
Solution Approach 1:
A phase-locked loop (PLL) is introduced as an intermediary device between the FIFO-fill signal and the recovered subscriber signal. The PLL filters the step-wise variations caused by stuff byte operations, producing a smooth recovered data clock signal that maintains accurate timing without the jitter introduced by rate adaptation operations.
Solution Approach 2:
The system employs feedback through the PLL mechanism where the recovered data clock is continuously compared with the original tributary clock, and the phase difference is used to adjust the clock output. This closed-loop feedback eliminates timing errors and maintains synchronization despite stuff byte insertions and extractions.
2Adaptability or versatility
If conventional mapping techniques are used to transport asynchronous traffic over synchronous networks, then network compatibility is improved, but timing accuracy deteriorates due to waiting time jitter
Solution Approach 1:
The PLL acts as a mediator that decouples the asynchronous nature of the tributary signal from the synchronous network requirements. It converts the jittery FIFO-fill signal into a clean recovered data clock that preserves original timing characteristics while enabling standard SONET/SDH mapping operations.
Solution Approach 2:
The patent replaces direct mechanical-style stuff byte insertion/extraction control with an electronic filtering approach using the PLL. Instead of directly controlling timing based on FIFO-fill signals, the system uses the PLL's natural filtering characteristics to eliminate jitter, substituting a more sophisticated electronic control mechanism.
Data Source
AI summary
A method of minimizing jitter in a system for rate adapting a data signal for transport through a synchronous network. A phase difference is measured between a data clock synchronous with the data signal and a local clock of the synchronous network. A timing reference (F) indicative of a frequency difference between the asynchronous data signal and the local clock is measured using the measured phase difference. Calculation of the timing reference includes compensating ambiguity in the measured phase difference.