Differential Delay Compensation in SONET SDH Virtual Concatenation
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Solution Overview
Problem
Differential delay in SONET/SDH communication networks, caused by virtual concatenation and pointer processing, complicates data reassembly at the receiver, requiring complex addressing and efficient memory management to align payload data correctly.
Innovation Solution
A method for differential delay compensation that involves recording physical and virtual write addresses for data frames, allowing continuous storage and efficient retrieval of data frames with the same Multiframe Indicator (MFI) value, enabling proper reassembly by calculating physical read addresses based on virtual read addresses and write addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored in memory at varying points for reassembly, then differential delay compensation is achieved, but addressing complexity increases
Solution Approach 1:
The patent segments the addressing process into two distinct components: virtual addresses that remain constant for each payload instance, and offset values that account for differential delays. This segmentation allows the complex physical addressing to be broken down into manageable parts, where the virtual address identifies the logical position and the offset compensates for timing variations, thereby reducing overall addressing complexity while maintaining reassembly accuracy.
Solution Approach 2:
The patent introduces a virtual address as an intermediary layer between the simple sequential write position and the complex physical read position. This virtual address acts as a mediator that decouples the write operation from the read operation, allowing data to be written at varying physical points while maintaining a consistent logical addressing scheme, thus reducing addressing complexity without sacrificing reliability.
2Reliability
If data is read and written at varying points in memory, then differential delay is compensated, but memory management complexity increases
Solution Approach 1:
The patent implements dynamic memory management where the read position is calculated based on the write position plus an offset value that varies depending on the differential delay experienced by each payload instance. This dynamic approach allows the system to adapt to varying delay conditions while maintaining systematic control through the offset calculation mechanism, thereby improving memory management ease without compromising reassembly accuracy.
Solution Approach 2:
The patent changes the parameter used for memory addressing from a fixed physical address to a variable offset value that is added to the virtual address. This parameter change allows the system to handle varying delay conditions by adjusting the offset rather than redesigning the entire addressing scheme, thus simplifying memory management operations while maintaining data reassembly accuracy.
3Manufacturing precision
If complex addressing is used to align payload data, then reassembly accuracy improves, but processing time increases
Solution Approach 1:
The patent performs preliminary calculation of the offset value based on known differential delay characteristics before the actual read operation. By pre-calculating the offset that needs to be applied to each virtual address, the system avoids complex real-time calculations during data retrieval, thus maintaining high alignment precision while reducing processing time.
Solution Approach 2:
The patent replaces complex mechanical-style addressing operations with a simpler mathematical calculation approach. Instead of using complex addressing logic that would require multiple conditional checks and iterations, the system uses a straightforward offset addition operation that can be performed rapidly, thereby reducing processing time while maintaining alignment precision.
Data Source
AI summary
In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.