Time Multiplexed SONET Line Processing Shared Circuitry
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Solution Overview
Problem
Existing SONET signal processing technologies require significant hardware multiplication to handle multiple signals, which is inefficient and not scalable for different combinations of SONET signals.
Innovation Solution
The solution involves time multiplexed processing of multiple SONET signals using shared circuitry for framing, descrambling, maintenance signal processing, control byte processing, and retiming, with signals being deserialized and multiplexed onto a byte-wide bus, allowing up to forty-eight STS-1 signals to be processed virtually concurrently through shared pipelines, each capable of handling multiple streams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple SONET signals are processed using separate dedicated circuits for each signal, then processing reliability and speed are improved, but hardware complexity and cost increase significantly
Solution Approach 1:
The patent merges multiple SONET signal processing functions into shared circuits. Specifically, framing circuits, descrambling circuits, maintenance signal processing circuits, control byte processing circuits, pointer tracking circuits, and retiming circuits are all shared across multiple SONET signals. This combining approach allows the system to process multiple signals (e.g., OC-3, OC-12, OC-48) using a single set of processing circuits rather than requiring separate dedicated circuits for each signal, thereby reducing hardware multiplication while maintaining processing capability.
Solution Approach 2:
The patent implements universal processing circuits that can handle multiple types of SONET signals. The shared circuits are designed to be signal-type agnostic, capable of processing OC-3, OC-12, OC-48, and other SONET signal formats through the same hardware infrastructure. This multi-functionality is achieved through configurable processing logic that can adapt to different signal types without requiring dedicated hardware for each signal format, thus improving hardware utilization efficiency.
2Reliability
If dedicated hardware is allocated for each SONET signal type, then processing reliability is improved, but adaptability to different signal combinations deteriorates
Solution Approach 1:
The patent implements dynamic signal processing where the shared circuits can be configured and reconfigured based on the specific SONET signal types and combinations being processed. The system dynamically adapts its processing behavior through configurable parameters and control logic that can handle different signal formats (OC-3, OC-12, OC-48, etc.) and their various combinations. This dynamic configuration capability allows the same hardware to reliably process diverse signal types without requiring dedicated static hardware for each signal type.
Solution Approach 2:
The patent utilizes parameter changes to enable the shared circuits to adapt to different SONET signal types. By modifying processing parameters, timing configurations, and control settings rather than changing the physical hardware, the system can reliably process different signal formats. This parameter-based adaptability allows the same circuitry to be reconfigured for different signal types and combinations, maintaining reliability while improving versatility.
3Device complexity
If shared circuits are used for multiple SONET signals, then hardware requirements are minimized, but processing time for each signal may increase due to sharing
Solution Approach 1:
The patent implements preliminary action through pre-configurable shared circuits that are prepared to handle multiple SONET signal types. The circuits include pre-loaded timing parameters, pre-configured processing logic, and pre-established data paths that enable rapid switching between different signal types. This preliminary preparation ensures that when a signal needs processing, the shared circuits are already optimized and ready, minimizing the time penalty that would otherwise result from reconfiguration delays.
Solution Approach 2:
The patent maintains continuity of useful action by ensuring that the shared circuits continuously process signals without idle time or reconfiguration delays. The system is designed so that the shared framing circuits, descrambling circuits, and other processing circuits remain in an active processing state, seamlessly transitioning between different SONET signal types without stopping or resetting. This continuous operation minimizes processing time loss while still allowing the circuits to serve multiple signal types.
Data Source
AI summary
Time multiplexed processing of multiple SONET signals uses the same shared circuitry for framing, descrambling, maintenance signal processing, control byte processing and extraction, pointer tracking, retiming, and alarm indication. The signals are deserialized and multiplexed onto a byte-wide bus from which they are processed in a shared pipeline. Additional pipelines allow scaling up to higher capacity SONET signals. Each pipeline is provided with means for communicating with the other pipelines so that information derived from the processing of one stream can be shared with the processing of other streams when necessary. According to the presently preferred embodiment, bytes pass through the pipeline in five clock cycles.