SONOS Analog Memory Biasing for Tight VT and ID Distributions
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Solution Overview
Problem
Existing non-volatile memory technologies, such as SONOS, struggle to achieve precise tuning of multiple threshold voltage (VT) and drain current (ID) levels with tight distributions, which is essential for analog operations and neuromorphic computing in artificial intelligence applications.
Innovation Solution
The method involves optimizing biasing conditions and operation sequences for SONOS-based non-volatile memory devices, including partial program and erase operations, to achieve precise control of VT and ID levels, using techniques like soft erase, refill program, and anneal erase operations, which allow for the storage of multiple analog values with low sigma distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional SONOS memory operations are used, then binary data storage is achieved, but multiple analog values with tight distributions cannot be stored
Solution Approach 1:
The patent applies dynamics by making the memory device's operational characteristics adjustable through controlled charge trapping and release mechanisms. By dynamically controlling the amount of charge trapped in the nitride layer through optimized biasing conditions and operation sequences, the device can achieve multiple distinct VT and ID levels with tight distributions, enabling analog operations while maintaining binary storage capability
Solution Approach 2:
The patent changes key operational parameters including biasing conditions (voltage magnitudes and polarities), operation durations, and sequence timing to precisely control charge trapping and release. These parameter changes enable the SONOS device to achieve multiple analog values with tight VT and ID distributions, transforming it from a binary to an analog-capable memory device
2Adaptability or versatility
If multiple VT levels are achieved, then analog storage capability improves, but VT distribution width increases
Solution Approach 1:
The patent applies preliminary action by performing optimization and characterization of biasing conditions and operation sequences before actual analog memory operations. Through preliminary experiments, the optimal voltage magnitudes, polarities, and timing parameters are established to achieve tight VT distributions across multiple levels, ensuring consistent analog performance
Solution Approach 2:
The patent implements feedback mechanisms through verification reads after program and erase operations. By measuring the actual VT and ID levels and comparing them to target values, the system can adjust subsequent operation parameters to maintain tight distributions, enabling precise control of multiple analog levels
3Measurement precision
If precise VT control is achieved, then analog operation precision improves, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the complex programming process into distinct program and erase operations with specific biasing conditions. Each operation targets specific charge trapping or release mechanisms, allowing independent optimization of each step to achieve overall precise VT control while managing complexity through modular operation sequences
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the storage of multiple analog values with tight and distinct VT/ID level distributions, improving the precision and reliability of analog operations in neuromorphic computing, while maintaining low power consumption and noise operations.
Implementation Method 1
a positive gate-to-substrate voltage bias causes electrons to tunnel from the channel and trapped in a charge-trapping dielectric layer by Fowler-Nordheim (FN) tunneling
Implementation Method 2
trapped in a charge-trapping dielectric layer, raising a threshold voltage (VT) of the transistor
Data Source
AI summary
A method of operating a semiconductor inference device that includes the steps of writing one of multiple analog weight values to memory cells of a non-volatile memory (NVM) array, receiving inputs through a bus system, performing multiply accumulate (MAC) operations based on the inputs and the stored analog weight values, converting results of the MAC operations to outputs, and transmitting the outputs through the bus system.