Embedded SONOS Memory Back-to-Back Gate Layout for Smaller Chips
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Solution Overview
Problem
Existing SONOS memory devices occupy large chip design area and have complex external circuit designs due to their two-transistor separated structure.
Innovation Solution
The embedded SONOS memory integrates selection and memory transistor polysilicon gates in a back-to-back structure, using connecting layers to connect the gate of the selection transistor to the substrate, and employs polysilicon gate self-aligned etching to define gate widths, with a hard mask to simplify circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If SONOS memory devices use a two-transistor separated structure, then the device can be manufactured with existing processes, but the chip design area becomes too large
Solution Approach 1:
The patent merges the selection transistor and memory transistor into a single integrated structure where the selection transistor gate and memory transistor gate are formed adjacently in the same trench. This integration reduces the chip design area while maintaining compatibility with existing manufacturing processes through standardized material layers and formation steps.
Solution Approach 2:
The patent implements a nested structure where the selection transistor components are embedded within the same trench and substrate region as the memory transistor. The selection transistor gate is formed in the trench alongside the memory transistor gate, with both structures sharing common isolation and substrate regions, thereby nesting functional elements to minimize area.
2Reliability
If the source end and gate of the selection transistor are connected to peripheral circuits separately, then the device structure is complete, but the external circuit design becomes more complicated
Solution Approach 1:
The patent combines the connection paths for the selection transistor source end and gate into a unified peripheral circuit interface. By forming the selection transistor gate adjacently to the memory transistor gate in the same trench, both gates can be connected to the same peripheral circuit node, simplifying external circuit design while maintaining complete device functionality.
Data Source
AI summary
An embedded SONOS memory and a method for making the same. The method includes: forming a connecting layer on one side of a selection transistor polysilicon gate; forming a second silicon oxide layer and an ONO charge storage layer on the other side of the selection transistor polysilicon gate far away from the connecting layer; then forming a memory transistor polysilicon gate on the side of the second silicon oxide layer far away from the connecting layer, so as to obtain the selection transistor polysilicon gate and the memory transistor polysilicon gate in a back-to-back structure.