SONOS Byte-Erasable EEPROM Refresh Control
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Solution Overview
Problem
Traditional byte-erasable EEPROMs based on floating gate tunnel oxide technology have large cell sizes, require many manufacturing steps, high operating voltages, and are not logic-process based, making them costly and unsuitable for data-intensive applications, while existing SONOS technology is only used in flash memory and suffers from write-disturb issues in byte-erasable EEPROMs.
Innovation Solution
A SONOS-based byte-erasable EEPROM array that uses a standard CMOS logic process to reduce costs and incorporates a refresh operation to prevent write-disturb in unselected memory cells, maintaining data integrity by recovering original data states after each erase and program cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If SONOS technology is used in byte-erasable EEPROM, then manufacturing cost is reduced and logic compatibility is improved, but write-disturb issues occur in unselected cells
Solution Approach 1:
The patent applies preliminary action by performing a refresh operation on unselected cells before they suffer data loss from write-disturb. The controller proactively detects and corrects threshold voltage shifts in unselected cells during the erase and program sequences, preventing data integrity degradation before it occurs.
Solution Approach 2:
The patent implements feedback by continuously monitoring the threshold voltage of unselected cells during erase and program operations. The controller adjusts inhibit voltages dynamically based on detected threshold voltage shifts, creating a closed-loop control system that maintains data integrity in unselected cells.
2Object-affected harmful factors
If inhibit voltages are applied to unselected cells, then erase-disturb and program-disturb are reduced, but write-disturb accumulates over time
Solution Approach 1:
The patent applies preliminary action by proactively refreshing unselected cells before their threshold voltage shifts become significant. The controller performs refresh operations on unselected cells during the erase and program sequences, preventing data loss before it occurs rather than waiting for disturbances to accumulate.
Solution Approach 2:
The patent implements periodic action by repeatedly applying refresh operations to unselected cells throughout the erase and program sequences. The controller periodically selects and refreshes unselected cells based on their threshold voltage status, preventing cumulative write-disturb effects.
3Adaptability or versatility
If byte-erasable EEPROM operations are performed frequently, then data storage flexibility is improved, but accumulated disturb time changes unselected cell data
Solution Approach 1:
The patent implements feedback by continuously monitoring threshold voltage shifts in unselected cells during frequent erase and program operations. The controller dynamically adjusts inhibit voltages and refresh operations based on real-time detection of disturb effects, maintaining data stability even with frequent operations.
Solution Approach 2:
The patent applies preliminary action by proactively refreshing unselected cells before frequent operations cause cumulative data loss. The controller anticipates write-disturb effects and performs refresh operations in advance, preventing data integrity degradation from frequent byte-erasable operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a low-cost, high-flexibility byte-erasable EEPROM with reduced array size and manufacturing complexity, effectively addressing write-disturb issues and ensuring data integrity by eliminating erase-disturb effects through the refresh operation.
Implementation Method 1
The memory cells include a charge-trapping layer, such as a silicon-oxide-nitride-oxide-silicon (SONOS) layer
Implementation Method 2
the controller performs a refresh operation when programming selected memory cells to reduce write-disturb on unselected memory cells
Data Source
AI summary
A SONOS byte-erasable EEPROM is disclosed. In one aspect, an apparatus includes a plurality of SONOS memory cells forming an EEPROM memory array. The apparatus also includes a controller that generates bias voltages to program and erase the memory cells. The controller performs a refresh operation when programming selected memory cells to reduce write-disturb on unselected memory cells to prevent data loss.