SONOS Memory Charge Trap Segmentation for Interference Reduction
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Solution Overview
Problem
In non-volatile SONOS memory devices, as cell size decreases, it becomes challenging to prevent charge interference between the source and drain regions due to the shared electric field across the charge trap and tunnel oxide layers, limiting integration density and retention time.
Innovation Solution
A charge trap layer is physically separated using a buffer layer, allowing independent electric fields for the charge trap and tunnel oxide layers, preventing charge movement between the source and drain regions, and enabling reduced cell size without interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cell size is reduced to increase integration density, then integration density is improved, but charge interference between source and drain regions increases
Solution Approach 1:
The charge trap layer is divided into two separate regions by introducing an intermediate layer (such as SiO2 or SiN) between the source and drain sides. This segmentation physically isolates the charges trapped on each side, preventing charge interference while maintaining high integration density through the reduced cell size.
Solution Approach 2:
An intermediate layer (SiO2 or SiN) is introduced between the source and drain regions of the charge trap layer. This intermediary layer acts as a barrier that prevents charge carriers from moving between source and drain, thereby eliminating charge interference while allowing the cell size to be reduced for higher integration density.
2Speed
If voltage is increased to improve write/erase speed, then operation speed is improved, but power consumption increases
Solution Approach 1:
The patent changes the material parameters of the tunnel oxide layer by using a thinner layer (5-10 nm) compared to conventional designs. This parameter change enables efficient charge injection at lower voltages, achieving high write/erase speeds without increasing power consumption, as the thinner oxide allows quantum tunneling to occur more readily at reduced voltage levels.
3Duration of action of moving object
If tunnel oxide thickness is increased to improve charge retention, then retention time is improved, but write/erase voltage requirement increases
Solution Approach 1:
The patent optimizes the tunnel oxide thickness to a specific range (5-10 nm) that balances charge retention and voltage requirements. Additionally, the use of a charge trap layer with specific material composition (SiN or SiO2) and the introduction of an intermediate layer create a structured design that enhances charge retention while maintaining manageable write/erase voltage levels through controlled charge trapping mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This separation enhances charge retention and integration density by preventing charge interference, enabling lower voltage, lower power, and high-speed operation in SONOS memory devices.
Implementation Method 1
the charges stored in the nitride layer 12 are moved toward the semiconductor substrate 10 by means of a Fowler-Nordheim (F—N) tunneling current through the tunnel oxide layer 11
Implementation Method 2
in SONOS, direct tunneling oxide is formed under the nitride layer. It is therefore possible to implement a memory device having a lower voltage, lower power and high-speed operation
Data Source
AI summary
A non-volatile memory device having a Polysilicon Oxide Nitride Oxide Semiconductor (SONOS) structure in which a charge trap layer is separated physically in a horizontal direction, and a method of manufacturing the same. The charge trap layer that traps electric charges toward the source and the drain is physically divided. It can fundamentally prevent the charges at both sides from being moved mutually. It is therefore possible to prevent interference between charges at both sides although the cell size is reduced.