SONOS FinFET Memory Cell Integration With Shared Logic Gate Process
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Solution Overview
Problem
Current technologies face challenges in integrating memory processes with logic processes in silicon-oxide-nitride-oxide-silicon (SONOS) memory cells for FinFET, as they require separate fabrication steps for memory and logic regions, leading to increased complexity and cost.
Innovation Solution
A method is developed to form a silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET by simultaneously creating a control gate with a charge trapping layer and a selective metal gate, which covers the fin's memory and logic regions, allowing for the integration of memory and logic processes through shared materials and steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate fabrication steps are used for memory and logic regions, then each region can be optimized independently, but the overall process complexity and manufacturing cost increase
Solution Approach 1:
The patent combines memory and logic fabrication processes into a single integrated flow. The control gate with charge trapping layer and selective metal gate are formed simultaneously for both memory and logic regions using shared deposition and patterning steps, eliminating the need for separate fabrication sequences while maintaining region-specific functionality through material selectivity
Solution Approach 2:
The patent creates a universal fabrication process that serves dual purposes: forming control gates in memory regions and selective metal gates in logic regions. The same deposition chambers, patterning tools, and process sequences are used for both memory and logic device formation, making the process multi-functional while reducing overall complexity
2Manufacturing precision
If separate fabrication steps are used for memory and logic regions, then each region can be optimized independently, but manufacturing cost increases
Solution Approach 1:
The patent merges memory and logic fabrication into one process flow, utilizing the same deposition equipment, patterning tools, and process chambers for both device types. This consolidation reduces equipment utilization costs, decreases process overhead, and lowers manufacturing expenses while preserving the ability to optimize each region through selective material deposition
Solution Approach 2:
The patent develops a universal process platform that can manufacture both memory and logic devices using identical fabrication steps and equipment. This multi-functional approach maximizes equipment utilization, reduces per-unit manufacturing costs, and simplifies production planning while maintaining the capability to independently optimize each device region through material selection
3Reliability
If control gate with charge trapping layer is formed, then memory functionality is achieved, but additional process steps are required compared to standard logic gates
Solution Approach 1:
The patent combines the formation of control gates with charge trapping layers in memory regions with the formation of selective metal gates in logic regions into a single integrated process sequence. The charge trapping layer is deposited using the same atomic layer deposition equipment and process conditions as the high-k dielectric layers for logic gates, eliminating additional dedicated process steps while achieving memory functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces complexity, and enables the concurrent formation of memory and logic components on a fin, thereby integrating memory processes into logic processes, enhancing manufacturing efficiency and reducing costs.
Implementation Method 1
A charge trapping material and a control gate material are sequentially deposited to cover the fin and the substrate blanketly
Implementation Method 2
A dielectric layer and a gate electrode layer are sequentially deposited to cover the fin and the substrate blanketly
Data Source
AI summary
A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET includes a fin, a control gate and a selective metal gate. The fin is on a top surface of a substrate, wherein the fin has two sidewalls and a top surface, and the fin includes a memory region and a logic region. The control gate is disposed over the fin of the memory region and covers the two sidewalls and the top surface of the fin, wherein the control gate includes a charge trapping layer and a control electrode, wherein the charge trapping layer is sandwiched by the fin and the control electrode. The selective metal gate is disposed over the fin adjacent to the control gate and covers the two sidewalls and the top surface of the fin. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.