SONOS Flash Memory Sidewall Residue Prevention
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Solution Overview
Problem
The existing method for fabricating SONOS flash memory often results in polysilicon residue on the sidewall of the dielectric layer, leading to potential short circuits between memory cells due to anisotropy etching and rectangular sections of the dielectric and polysilicon layers.
Innovation Solution
The method involves selectively etching the first polysilicon layer to form an inverse trapezia section along the word line direction and filling a dielectric layer with a trapezia section, allowing for easy removal of polysilicon residue by vertical etching, preventing short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If anisotropy etching is used to fabricate the dielectric layer and polysilicon layer with rectangular sections, then the fabrication process is simplified and manufacturing efficiency is improved, but polysilicon residue forms on the sidewall of the dielectric layer causing short circuits between memory cells
Solution Approach 1:
The patent applies asymmetry by changing the cross-sectional shape of the dielectric layer and polysilicon layer from rectangular to trapezoidal. This asymmetric geometry with inclined sidewalls prevents polysilicon residue accumulation that occurs with vertical rectangular walls, thereby eliminating short circuits while maintaining fabrication efficiency through selective etching processes.
Solution Approach 2:
The patent utilizes curved inclined surfaces instead of sharp rectangular corners. The trapezoidal structure with sloped sidewalls creates a curved geometry that facilitates complete removal of polysilicon material during etching, preventing residue formation on sidewalls while preserving the simplified fabrication approach.
2Reliability
If selective etching is used to form the first polysilicon layer with an inverse trapezia section, then polysilicon residue on the dielectric layer sidewall is prevented, but the etching process complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-forming the inverse trapezia section in the first polysilicon layer before depositing the dielectric layer. This preliminary geometric configuration ensures that subsequent dielectric deposition and etching processes naturally produce the desired trapezoidal structure without requiring complex multi-step etching sequences, thereby preventing polysilicon residue while controlling process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents polysilicon residue formation on the sidewall of the dielectric layer, thereby avoiding short circuits between memory cells and enhancing the fabrication process of SONOS flash memory.
Implementation Method 1
due to anisotropy etching and rectangular sections of the dielectric and polysilicon layers
Implementation Method 2
An ion implantation is performed to the silicon substrate 100 through the ONO layer 102 by using the gate as a mask, to form the source/drain 101
Data Source
AI summary
A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) flash memory, comprising: preparing a silicon substrate including a silicon oxide-silicon nitride-silicon oxide (ONO) layer, a first polysilicon layer and a first etch stop layer in sequence; etching the first etch stop layer along a direction of bit line; selectively etching the first polysilicon layer with the first etch stop layer as a mask, till the silicon oxide-silicon nitride-silicon oxide (ONO) layer is exposed, the etched first polysilicon layer having an inverse trapezia section along a direction of word line; filling a dielectic layer between portions of the first polysilicon layer, the dielectric layer having a trapezia section along the direction of word line. After the above steps, it becomes easy to remove the portion of the first polysilicon layer on a sidewall of the dielectric layer by vertical etching. Thus, no polysilicon residue will be formed on the sidewall of the dielectric layer. Thereby, the short circuit between different memory cells may be avoided.