2T SONOS Memory Cell Gate-All-Around Structure
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Solution Overview
Problem
The integration of non-volatile memory in semiconductor devices poses challenges in achieving higher functionality and scalability, particularly in three-dimensional designs, where existing technologies struggle to efficiently integrate memory cells with precise control over memory operations and reduced device size.
Innovation Solution
The implementation of a two-transistor (2T) SONOS non-volatile memory cell with a gate-all-around (GAA) structure, which includes a select transistor and a control transistor, allows for precise control of memory operations and scalability by forming semiconductor wires with specific doping and dielectric layers, and replacing dummy gate structures with metal gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If floating gate designs are used, then memory functionality is achieved, but device size reduction and scalability are limited
Solution Approach 1:
The memory cell is divided into two separate transistors: a select transistor for controlling access to the memory cell and a control transistor for controlling memory operations (write/read/erase). This segmentation allows each transistor to be independently optimized and controlled, enabling precise memory operation control while reducing overall device size compared to floating gate designs.
Solution Approach 2:
The patent transitions from planar floating gate structures to vertically-oriented gate-all-around (GAA) structures where gate electrodes wrap around the semiconductor wire in three dimensions. This dimensional change enables better control over the memory cell while reducing the footprint area, achieving both size reduction and improved control precision.
2Productivity
If three-dimensional designs are implemented, then higher device density is achieved, but fabrication and design challenges increase
Solution Approach 1:
The three-dimensional memory cell is segmented into distinct functional components (select transistor, control transistor, semiconductor wire, tunnel barrier, charge trap layer, block dielectric) that can be independently formed and controlled. This segmentation simplifies the fabrication process by allowing sequential formation of each layer through standard semiconductor processing techniques, reducing overall fabrication complexity despite the 3D architecture.
Solution Approach 2:
The gate electrodes are nested around the semiconductor wire in a gate-all-around configuration, with the tunnel barrier, charge trap layer, and block dielectric also nested in concentric layers around the wire. This nested structure achieves high device density while using straightforward sequential deposition processes, managing fabrication complexity through modular layer-by-layer construction.
3Adaptability or versatility
If non-volatile memory is integrated, then higher functionality is achieved, but integration challenges with precise control increase
Solution Approach 1:
By separating the select function and control function into two distinct transistors, the patent enables independent optimization of each transistor's characteristics. The select transistor can be optimized for access control while the control transistor is optimized for memory operations, achieving precise control over write, read, and erase operations independently, thereby improving manufacturing precision for memory operations.
Solution Approach 2:
The control transistor acts as an intermediary between the control signals and the memory cell, providing precise control over charge injection and removal in the charge trap layer. This intermediary structure enables fine-tuned control of memory operations with reduced interference from selection signals, improving the precision of memory manufacturing and operation control.
Data Source
AI summary
A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.