2T SONOS Gate Isolation Structure for Breakdown Prevention
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Solution Overview
Problem
The challenge in non-volatile semiconductor memory development is to improve the isolation capability between the selection gate and storage gate structures in 2T SONOS memory cells to prevent data loss and ensure accurate data storage, especially as cell size reduction leads to performance degradation.
Innovation Solution
The implementation of a shallow indent isolation structure with a liner layer and dielectric fill between the gate structures, along with a silicide layer on the second gate structure, enhances the isolation distance and reduces the likelihood of breakdown between the memory gate and selection gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the cell size is reduced to increase storage capacity, then the storage capability increases, but the isolation capability between gate structures deteriorates leading to data loss
Solution Approach 1:
The isolation structure is divided into multiple segments: a first isolation structure between the memory gate and selection gate, and a second isolation structure between the control gate and selection gate. This segmentation allows each isolation structure to be independently optimized for its specific function, improving overall isolation capability while maintaining compact cell size
Solution Approach 2:
Different isolation structures are applied at different locations based on local requirements. The first isolation structure (with greater width) is placed where stronger isolation is needed between memory gate and selection gate, while the second isolation structure is placed where moderate isolation suffices between control gate and selection gate, optimizing both isolation performance and space utilization
2Reliability
If the isolation distance between gate structures is increased to prevent breakdown, then the reliability improves, but the cell area increases reducing storage density
Solution Approach 1:
The isolation structures have different widths tailored to local isolation requirements. The first isolation structure has a greater width to provide stronger isolation between the memory gate and selection gate, while the second isolation structure has a smaller width sufficient for isolating the control gate from the selection gate, thereby preventing breakdown while minimizing overall cell area
Solution Approach 2:
The isolation structures extend in the horizontal direction between gate structures, utilizing the lateral dimension to provide isolation distance without increasing the vertical profile or requiring additional height, thus preventing breakdown while maintaining compact cell footprint
Data Source
AI summary
A method for fabricating memory device is provided. The method comprises forming a cell structure on a substrate, wherein the cell structure comprises a first gate structure and a second gate structure disposed on a substrate and an insulating layer in contact between the first gate structure and the second gate structure, wherein the first gate structure and the second gate structure are planarized and the first gate structure is for storing charges. Further, the first gate structure and the second gate structure are patterned to have a shallow indent above the insulating layer. An isolation structure is formed in the shallow indent to have a shallow indent isolation.