2T SONOS Memory Cell Gate Line Level Uniformity
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Solution Overview
Problem
Conventional 2T SONOS memory cell fabrication processes result in differing root levels for selection and control gate lines on shallow trench isolation structures, leading to poor performance and potential data loss due to defects in the control gate line.
Innovation Solution
The semiconductor memory device design ensures that the selection and control gate lines have the same bottom and top levels on the shallow trench isolation structure, with the STI structure being lower than the substrate, and a method involving implanting P-type impurities and etching to maintain uniform height and prevent defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conventional fabrication process is used for 2T SONOS memory cell, then the manufacturing process can be completed, but the selection gate line and control gate line have different root levels on the shallow trench isolation structure, causing poor performance and potential data loss
Solution Approach 1:
The patent applies preliminary action by forming the shallow trench isolation structure with a predetermined recess depth before forming the gate lines. The STI structure is recessed by a specific distance (20-40 angstroms) below the substrate surface, and gate lines are then formed over this pre-prepared structure. This preliminary preparation ensures that both selection and control gate lines start from the same root level, eliminating the performance issues caused by level differences while maintaining a streamlined fabrication process.
2Productivity
If the cell size is reduced to increase storage capability, then the memory volume can be reduced and storage capacity increased, but the memory cell performance deteriorates and data may be lost
Solution Approach 1:
The patent applies parameter changes by modifying the physical dimensions and positioning parameters of the gate lines and shallow trench isolation structure. Specifically, it controls the root level position and height of the gate lines relative to the STI structure, ensuring uniform starting levels. This parameter optimization maintains reliable data storage even as cell dimensions are reduced for higher capacity devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the performance of the 2T SONOS memory cell by ensuring consistent gate line levels and reducing defects, enhancing data storage reliability and capacity.
Implementation Method 1
an implanting process is performed on STI structures
Data Source
AI summary
A semiconductor memory device includes a substrate, having a plurality of cell regions, wherein the cell regions are parallel and extending along a first direction. A plurality of STI structures is disposed in the substrate, extending along the first direction to isolate the cell regions, wherein the STI structures have a uniform height lower than the substrate in the cell regions. A selection gate line is extending along a second direction and crossing over the cell regions and the STI structures. A control gate line is adjacent to the selection gate line in parallel extending along the second direction and also crosses over the cell regions and the STI structures. The selection gate line and the control gate line together form a two-transistor (2T) memory cell.