SONOS Flash Memory Gate Stack With Oxynitride Interface for Leakage Control
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Solution Overview
Problem
Existing SONOS flash memory devices face performance loss and reduced erase count due to a short channel effect at gate lengths below 50 nm, leading to instability and decreased stability.
Innovation Solution
A gate dielectric layer comprising a tunneling dielectric layer, a storage dielectric layer with a first and third silicon nitride layer, and a barrier dielectric layer, where a second interface layer of silicon oxynitride is inserted between the silicon nitride layers to reduce electron leakage and enhance stability, achieved by treating the first silicon nitride layer with oxygen and nitrogen.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the gate length is reduced below 50 nm to facilitate dense memory design, then memory density is improved, but the short channel effect enhances causing performance loss and reduced stability
Solution Approach 1:
The gate dielectric layer is segmented into multiple functional layers: tunneling dielectric layer, storage dielectric layer (with first and third silicon nitride layers), and barrier dielectric layer. This segmentation allows each layer to perform its specific function optimally, enabling reduced gate length while maintaining stability through the combined effect of multiple specialized layers rather than a single thick layer.
Solution Approach 2:
The patent uses composite dielectric structures combining different materials (oxide for tunneling and barrier, nitride for storage) with complementary properties. The oxide layers provide good interface quality and tunneling characteristics, while the nitride layers provide high electron trapping capability. This composite structure maintains device reliability at scaled dimensions by leveraging the strengths of each material.
2Device complexity
If a simple ONO structure is used as floating gate electrode, then manufacturing process is simplified, but electron leakage occurs reducing erase count and stability
Solution Approach 1:
The barrier dielectric layer (oxide layer) is introduced as an intermediary between the storage dielectric layer and the gate conductive layer. This intermediary layer prevents electron leakage from the storage layer to the gate, thereby improving erase count stability while maintaining a relatively simple overall structure that builds upon the conventional ONO architecture.
Solution Approach 2:
Different regions of the gate dielectric structure are assigned different materials and functions: the tunneling dielectric layer (oxide) provides electron injection capability, the storage dielectric layer (nitride) provides electron trapping capability, and the barrier dielectric layer (oxide) provides electron confinement. This local differentiation of properties allows the structure to prevent electron leakage without requiring complete redesign of the entire gate stack.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the reliability and stability of the storage transistor by reducing electron leakage and increasing the erase count, with a simple and cost-effective process.
Implementation Method 1
the second interface layer is used to reduce the outflow of the programming electrons out of the storage dielectric layer by means of the feature that the width of band gap of silicon oxynitride is greater than that of silicon nitride
Implementation Method 2
programming electrons are stored in the defect of the first silicon nitride layer and the defect of the third silicon nitride layer
Data Source
AI summary
The present application discloses a flash memory, wherein a gate dielectric layer of a storage transistor comprises a tunneling dielectric layer, a storage dielectric layer, and a barrier dielectric layer stacked in sequence. The storage dielectric layer includes a first silicon nitride layer, a second interface layer, and a third silicon nitride layer stacked in sequence. The material for the second interface layer is silicon oxynitride. With the storage transistor in a programming state, programming electrons are stored in the defect of the first silicon nitride layer and the defect of the third silicon nitride layer, and the outflow of the programming electrons out of the storage dielectric layer is reduced by means of the feature that the width of band gap of silicon oxynitride is greater than that of silicon nitride. The present application also discloses a method of making a flash memory.