L-Shaped SONOS Memory Gate Stack Non-Damascene Process
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Solution Overview
Problem
Conventional manufacturing processes for SONOS non-volatile memory devices are complex and expensive, such as damascene-based processes, which complicate the integration and scalability of these devices.
Innovation Solution
A non-damascene based manufacturing process is employed to form a gate stack with an oxide-nitride-oxide stack and semiconductor spacers, allowing for a single-contact design that simplifies the device structure and manufacturing, with a gate electrode and semiconductor spacers made of polysilicon, and a contact pad formed over and in electrical contact with the gate electrode and spacers, using a metal silicide or epitaxial silicon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If damascene-based processes are used for manufacturing SONOS devices, then manufacturing precision and reliability are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and eliminates the damascene process steps from the manufacturing flow, replacing them with a simplified approach where the oxide-nitride-oxide stack is formed directly without requiring the complex damascene trench formation and filling processes, thereby reducing manufacturing complexity while maintaining device reliability
Solution Approach 2:
The manufacturing process is segmented into distinct, simpler steps: forming the oxide-nitride-oxide stack, depositing semiconductor layers, and defining spacers through selective removal. This segmentation allows each step to be optimized independently without the interdependencies inherent in damascene processes, reducing overall process complexity
2Reliability
If conventional SONOS device structures are used, then non-volatile memory functionality is achieved, but device area and manufacturing cost increase
Solution Approach 1:
The patent introduces semiconductor spacers positioned laterally adjacent to the gate stack, creating a three-dimensional structure that utilizes vertical and lateral dimensions more efficiently. This dimensional optimization allows the device to maintain its non-volatile memory functionality while reducing the lateral footprint and overall device area
Solution Approach 2:
The oxide-nitride-oxide stack is nested within the gate structure, with the nitride layer positioned between oxide layers that are integrated with the gate electrode and substrate. This nested configuration maximizes the use of available space, allowing multiple functional layers to occupy overlapping vertical spaces, thereby reducing the overall device area
3Device complexity
If simplified manufacturing processes are used, then device complexity and cost are reduced, but manufacturing precision may deteriorate
Solution Approach 1:
The patent specifies precise parameter ranges for the oxide-nitride-oxide stack layers, with the first oxide layer at about 50 Å, the nitride layer at about 70 Å, and the second oxide layer at about 70 Å. These controlled parameter specifications ensure manufacturing precision is maintained even though the overall process complexity is reduced, as each layer's thickness is tightly controlled during deposition
Data Source
AI summary
A non-volatile semiconductor memory device includes a gate stack formed on a substrate, semiconductor spacers, an oxide-nitride-oxide stack, and a contact pad. The semiconductor spacers are adjacent to sides of the gate stack and over the substrate. The oxide-nitride-oxide stack is located between the spacers and the gate stack, and located between the spacers and the substrate, such that the oxide-nitride-oxide stack has a generally L-shaped cross-section on at least one side of the gate stack. The contact pad is over and in electrical contact with the gate electrode and the semiconductor spacers. The contact pad may be further formed into recessed portions of the oxide-nitride-oxide stack between the gate electrode and the semiconductor spacers. The contact pad may include an epitaxial silicon having a metal silicide formed thereon.