SONOS Gate Stack Segmentation for Leakage Control
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Solution Overview
Problem
Conventional SONOS memory devices face significant leakage issues due to thin tunneling oxide layers, which compromise charge retention and erase efficiency, as stored charges are more likely to leak to the substrate through thin layers.
Innovation Solution
The implementation of a SONOS memory device structure with a silicon-rich layer, an oxygen-rich layer, and a nitrogen-rich layer, where the silicon-rich layer is the thinnest, the oxygen-rich layer is thicker, and the nitrogen-rich layer has high trap density, forming a stacked structure that enhances charge retention and reduces erase voltage by controlling band edges and tunneling mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the thickness of the tunneling oxide layer is decreased to scale down erase voltages, then erase voltage is reduced, but charge leakage increases significantly
Solution Approach 1:
The patent divides the storage layer into multiple distinct layers (conductive storage layer, insulating storage layer, and charge trapping layer) with different functions. The insulating storage layer segments the charge storage function from the tunneling function, allowing thin tunneling oxide for low erase voltage while preventing charge leakage through proper layer design.
Solution Approach 2:
The insulating storage layer acts as an intermediary between the thin tunneling oxide layer and the charge trapping layer. This intermediary layer prevents direct charge leakage paths while still allowing the thin tunneling oxide to function effectively for low-voltage operation.
2Quantity of substance
If a conductive storage layer is used in conventional SONOS, then charge storage is achieved, but leakage to substrate increases through thin tunneling oxide
Solution Approach 1:
The patent applies different material properties to different layers: the conductive storage layer provides charge storage capability where needed, the insulating storage layer provides electrical isolation to prevent leakage, and the charge trapping layer provides charge retention. Each layer has locally optimized properties for its specific function.
Solution Approach 2:
The storage structure uses a composite of multiple materials with different electrical properties - conductive materials for charge storage, insulating materials for charge isolation, and charge trapping materials for retention. This composite structure achieves both charge storage and leakage prevention simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces leakage, prolongs retention time, and enables a faster erase operation with lower erase voltage, while being compatible with existing CMOS processes.
Implementation Method 1
a tunneling layer; a first layer; a second layer; a third layer; and a blocking layer
Implementation Method 2
the nitrogen-rich layer has high trap density, forming a stacked structure that enhances charge retention
Data Source
AI summary
A memory device is disclosed. The memory device includes a substrate, including a substrate, including a source region and a drain region; and a gate stack, formed over a surface of the substrate, wherein the gate stack includes: a tunneling layer; a first layer; a second layer; a third layer; and a blocking layer; wherein each of the tunneling layer and the blocking layer has an oxygen proportion higher than the first, the second and the third layers; the first layer has a highest silicon proportion among the first, the second and the third layers; the second layer has a highest oxygen proportion among the first, the second and the third layers; and the first layer has a highest nitrogen proportion among the first, the second and the third layers. An associated gate stack and a manufacturing method are also disclosed.