SONOS Memory 3-Bit Storage via Charge Region Segmentation
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Solution Overview
Problem
Conventional multi-bit memory devices face issues with erroneous detection and inferior reliability due to the need for large voltage differences between threshold voltages and precise electron injection, which complicates operations and increases production costs.
Innovation Solution
A method for operating a memory device that stores 3-bit information by charging different regions of a charge storage layer above the source, drain, and channel, using Fowler-Nordheim tunneling and channel hot electron injection to determine programmed/erased states, allowing for increased memory density and reduced production costs without additional process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional multi-level cell technique is used to achieve multi-bit storage, then the number of bits per cell can be increased, but the voltage difference between threshold voltages must be large enough which complicates operations and reduces reliability
Solution Approach 1:
The charge storage layer is segmented into multiple distinct regions (first region above source, second region above drain, third region above channel) that can be independently programmed and read. This segmentation allows each region to store one bit of information independently, achieving 3-bit storage per cell without requiring large voltage differences between threshold voltages, thereby improving reliability while increasing storage capacity
Solution Approach 2:
Instead of using multiple threshold voltages along a single voltage dimension, the invention transitions to a spatial dimension by distributing charge storage across three distinct physical regions above different transistor components (source, drain, channel). This dimensional change enables multi-bit storage through spatial separation rather than voltage differentiation, simplifying read operations and improving detection accuracy
2Quantity of substance
If conventional multi-level cell technique is used with precise electron injection control, then multi-bit storage can be achieved, but the operations become complex and production costs increase
Solution Approach 1:
The charge storage layer is segmented into multiple distinct regions (first region above source, second region above drain, third region above channel) that can be independently programmed and read. This segmentation allows each region to store one bit of information independently, achieving 3-bit storage per cell without requiring large voltage differences between threshold voltages, thereby improving reliability while increasing storage capacity
Solution Approach 2:
Instead of using multiple threshold voltages along a single voltage dimension, the invention transitions to a spatial dimension by distributing charge storage across three distinct physical regions above different transistor components (source, drain, channel). This dimensional change enables multi-bit storage through spatial separation rather than voltage differentiation, simplifying read operations and improving detection accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances memory density, reduces production costs, and improves reliability by allowing 3-bit storage in a single transistor with reduced erroneous detection, while being compatible with existing techniques and manufacturing processes.
Implementation Method 1
applying a first positive voltage to the gate for injecting electrons into the channel storage region by FN tunneling
Implementation Method 2
applying a first negative voltage to the gate for removing electrons from the channel storage region by FN tunneling
Implementation Method 3
applying a second positive voltage and a third positive voltage to the gate and the drain respectively for injecting electrons into the drain storage region by channel hot electron injection
Implementation Method 4
applying a fourth positive voltage to the drain for removing electrons from the drain storage region by FN tunneling
Implementation Method 5
applying a fifth positive voltage and a sixth positive voltage to the gate and the source respectively for injecting electrons into the source storage region by channel hot electron injection
Implementation Method 6
applying a seventh positive voltage to the source for removing electrons from the source storage region by FN tunneling
Data Source
AI summary
A method for operating a memory device is provided. In accordance with the method, the charges are stored in a source storage region, a drain storage region, and a channel storage region of a charge storage layer which respectively correspond to a source, a drain, and a channel of a SONOS transistor, thereby achieving 3-bit information storage in one cell. The channel storage region is programmed and erased by FN tunneling. Both of the source storage region and the drain storage region are programmed by channel hot electrons and erased by source-side or drain-side FN tunneling. The present invention can store three-bit data per cell, such that the storage density of the memory device can be substantially increased.