1.5T SONOS Memory Cell Area Reduction via Shared Source-Drain
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Solution Overview
Problem
Existing 2T SONOS nonvolatile memory cell structures occupy a large area due to complete source and drain regions, necessitating a reduction in size while maintaining functionality.
Innovation Solution
The proposed solution involves a 1.5T SONOS nonvolatile memory cell structure design where adjacent memotrons and selectrons share source-drain regions, with gate structures defined through self-alignment and photo-etching minimized, allowing for reduced area occupation and lower process costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complete source and drain regions are configured for both memotron and selectron, then device functionality is maintained, but area occupied increases
Solution Approach 1:
The patent merges the source/drain regions of adjacent memotrons by sharing common regions. Specifically, the drain region of one memotron serves as the source region for the adjacent memotron, eliminating redundant regions and reducing overall cell area while maintaining complete source-drain functionality for each transistor.
Solution Approach 2:
The shared source-drain regions serve multiple functions simultaneously - they act as drain for one transistor and source for the adjacent transistor, enabling region multi-functionality that reduces the total number of required regions from four to two per cell structure.
2Ease of manufacture
If self-aligned gate structures are implemented, then photoetching steps are minimized, but manufacturing precision requirements increase
Solution Approach 1:
The gate structures are formed with preliminary self-alignment features during the deposition and etching processes. The polysilicon gates are patterned to inherently define the boundaries of source-drain regions, eliminating the need for subsequent photoetching steps to define these boundaries and reducing alignment precision requirements.
Data Source
AI summary
A SONOS nonvolatile memory includes a second gate structure of a selectron isolated from a first gate structure of a memotron by an inter-gate dielectric isolation layer formed on a first side of the first gate structure through self-alignment. The second gate structure is formed on a first side of the inter-gate dielectric isolation layer through self-alignment. A cell structure is formed by two adjacent cell structures. A first window defines an area formed by the two first gate structures. Two sides of each first gate structure are defined through self-alignment by first top silicon nitride layers formed on inner sides of the first window. First silicon nitride spacers are formed on second sides of the first gate structures through self-alignment. The bottom area of a contact hole between the second sides of the first gate structures is defined through self-alignment by the two first silicon nitride spacers.