SONOS Memory Structure With Composite SOI Substrate
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Solution Overview
Problem
Current SONOS memory technology faces challenges in reducing transistor size and improving leakage characteristics and uniformity, as it relies on the conventional bulk silicon process, which is incompatible with SOI technology, leading to increased wafer surface area occupation and complex manufacturing processes.
Innovation Solution
A SONOS memory structure and manufacturing method that incorporates a composite substrate with a buried oxide layer and surface silicon layer, featuring silicon epitaxial layers and spacers to form compact select transistor gates adjacent to the memory transistor gate, reducing wafer surface area and enhancing leakage performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional bulk silicon process is used for SONOS memory, then manufacturing process is well-established, but wafer surface area occupation increases and leakage characteristics deteriorate
Solution Approach 1:
The patent transitions from planar transistor layout to three-dimensional stacked architecture, where select transistors are positioned vertically above the memory transistor. This vertical stacking in the Z-dimension reduces the horizontal footprint on the wafer surface while maintaining all necessary transistor functions, directly resolving the contradiction between manufacturing maturity and area reduction.
Solution Approach 2:
The patent implements a nested structure where select transistor gates are formed above and around the memory transistor gate, creating a compact integrated structure. The control gates are positioned in a nested arrangement that maximizes space utilization and reduces overall cell area while maintaining electrical isolation and functionality.
2Ease of manufacture
If conventional bulk silicon process is used for SONOS memory, then manufacturing process is well-established, but leakage characteristics worsen
Solution Approach 1:
The patent employs a composite substrate structure combining SOI (Silicon-On-Insulator) technology with SONOS memory stack. The buried oxide layer in the SOI substrate provides excellent electrical isolation that suppresses leakage current, while the SONOS structure (Silicon-Oxide-Nitride-Oxide-Silicon) provides charge trapping capability. This composite approach integrates the leakage suppression benefits of SOI with the memory functionality of SONOS.
Solution Approach 2:
The patent introduces an intermediary buried oxide layer between the silicon substrate and the active device region. This oxide layer acts as a mediator that blocks substrate leakage paths while allowing the memory transistor to function properly. The intermediary layer provides electrical isolation without interfering with the memory storage mechanism.
3Productivity
If transistor size is reduced to increase density, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent addresses manufacturing precision challenges by moving from two-dimensional scaling to three-dimensional stacking. Instead of reducing transistor dimensions in the plane (which demands higher precision), the design exploits the vertical dimension to achieve density improvement. This approach relaxes lateral precision requirements while maintaining functional integrity through the stacked architecture.
Solution Approach 2:
The patent segments the memory cell into distinct functional layers stacked vertically: memory transistor layer, select transistor layer, and control gate layer. This segmentation allows each layer to be optimized and fabricated with standard precision requirements, avoiding the need for ultra-high precision in a single planar structure. The modular stacked design enables incremental fabrication with conventional processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in a more compact SONOS memory cell with improved leakage characteristics and uniformity, reducing the surface area occupied by the memory cell and simplifying the manufacturing process while maintaining superior electrical performance.
Implementation Method 1
a charge-trapping gate-dielectric layer in the memory transistor gate electrode
Implementation Method 2
electrically isolated from the memory transistor gate electrode by sidewall spacers
Data Source
AI summary
The present disclosure provides a SONOS memory structure and a manufacturing method therefor. The SONOS memory structure including a substrate and a select transistor gate and a memory transistor gate formed on the substrate, wherein the substrate is a composite substrate including a base silicon layer, a buried oxide layer and a surface silicon layer, wherein the upper portion of the base silicon layer has a memory transistor well region formed therein; the select transistor gate and the memory transistor gate are formed on the surface silicon layer; the select transistor gate comprises a first select transistor gate and a second select transistor gate, the first select transistor gate and the second select transistor gate are respectively located at two sides of the memory transistor gate, and are electrically isolated from the memory transistor gate by first spacers on both sides of the memory transistor gate.