SONOS Memory Cell in SOI with Divided Bit Line Architecture
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Solution Overview
Problem
Current flash memory technologies, such as NOR and NAND architectures, face limitations in supporting high-speed random access read and write operations due to power consumption, endurance issues, and scalability challenges, while dynamic random access memory (DRAM) faces difficulties in data retention and power requirements.
Innovation Solution
The development of a silicon-oxide-nitride-oxide-silicon (SONOS)-type memory structure in Silicon-On-Insulator (SOI) technology with a divided bit line architecture, allowing for parallel connection of memory cells for fast read operations, low-power Fowler-Nordheim tunneling, and random erase capabilities, along with a 'SONS' structure without tunnel oxide for high-speed program/erase operations and improved endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If NOR Flash architecture is used with parallel transistor connections to achieve fast random access read, then reading speed is improved, but power consumption increases due to channel hot electron injection
Solution Approach 1:
The invention segments the memory array into multiple blocks with independent bit line pairs, allowing selective activation of only the required block during read operations. This reduces the overall power consumption while maintaining fast random access read capability by limiting the active transistor count in each operation.
Solution Approach 2:
The patent implements local quality by providing independent source and drain lines for each column of cells within blocks, enabling localized read operations. This allows the memory system to activate only the specific bit line pair needed for the read operation, reducing power consumption while maintaining fast access speed for the selected cell.
2Use of energy by moving object
If NAND Flash architecture is used with series transistor connections to reduce power consumption, then power consumption is reduced, but reading speed decreases due to current flowing through all series cells
Solution Approach 1:
The invention divides the memory into multiple blocks where each block contains transistors connected in parallel rather than series. This segmentation allows current to flow through multiple parallel paths simultaneously, achieving fast read speeds while maintaining low power consumption by activating only the necessary block.
Solution Approach 2:
The patent transitions from the traditional series connection (one-dimensional current path) to a parallel block structure (multi-dimensional current paths). By organizing memory cells into parallel blocks with independent bit lines, the invention enables current to flow through multiple paths simultaneously, achieving both fast read speed and low power consumption.
3Quantity of substance
If conventional DRAM scaling is continued to increase density, then memory density is improved, but data retention deteriorates due to reduced cell capacitance
Solution Approach 1:
The invention introduces a charge trapping layer as an intermediary between the tunnel oxide and the channel. This charge trapping layer stores charge more reliably than conventional capacitor structures, enabling data retention without requiring large capacitance. This allows continued scaling for higher density while maintaining reliable data storage.
Solution Approach 2:
The patent changes the fundamental storage mechanism from capacitor-based charge storage to charge trapping in a dielectric layer. This parameter change in the storage mechanism allows for much smaller cell sizes (improved density) while maintaining or even improving data retention characteristics, as the trapped charge is more stable than capacitor-held charge.
4Speed
If ultra-thin tunnel oxide is used in SONOS devices to achieve fast program/erase speed, then program/erase speed is improved, but oxide damage increases due to direct tunneling current
Solution Approach 1:
The invention introduces a charge trapping layer as an intermediary between the tunnel oxide and the channel, preventing direct current flow through the tunnel oxide during program and erase operations. Charge is injected into or extracted from the trapping layer without passing significant current through the oxide, thus maintaining oxide integrity and endurance while achieving fast program/erase speeds.
Solution Approach 2:
The patent uses the charge trapping layer as a copy or intermediate storage mechanism. Instead of directly tunneling charge through the thin oxide (which causes damage), the system copies charge into the trapping layer through a controlled process, achieving the desired program/erase function while protecting the oxide from degradation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables high-density, high-speed random access and nonvolatile memory applications with superior scaling capability, high endurance, and low power consumption, supporting both dynamic random access and nonvolatile storage with enhanced data retention.
Implementation Method 1
low-power Fowler-Nordheim tunneling
Implementation Method 2
Direct tunneling through thin oxide provides fast program/erase speed at low voltage
Data Source
AI summary
Silicon-oxide-nitride-oxide-silicon SONOS-type devices (or BE-SONOS) fabricated in Silicon-On-Insulator (SOI) technology for nonvolatile implementations. An ultra-thin tunnel oxide can be implemented providing for very fast program/erase operations, supported by refresh operations as used in classical DRAM technology. The memory arrays are arranged in divided bit line architectures. A gate injection, DRAM cell is described with no tunnel oxide.