SONOS Memory Cell Segmentation for Bit-Line Disturb Reduction
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Solution Overview
Problem
Conventional SONOS memory technologies experience significant reliability issues due to 'bit line disturb' and 'inhibit disturb' effects during programming and erase operations, leading to threshold voltage shifts and potential cell read failures over time.
Innovation Solution
The implementation of a two-transistor memory cell structure with a SONOS-type memory transistor and a select transistor, where the bit line disturb voltage is reduced by increasing the inhibit voltage, effectively equalizing the cumulative bit line disturb with a single inhibit disturb, thereby stabilizing the threshold voltage shifts and extending memory cell endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SONOS memory structure is used, then manufacturing simplicity is maintained, but bit line disturb and inhibit disturb effects cause threshold voltage shifts and reliability degradation
Solution Approach 1:
The memory cell is divided into two separate transistors: a first transistor for programming operations and a second transistor for read operations. This segmentation isolates the disturb effects from the read operation, allowing the read transistor to operate without experiencing threshold voltage shifts caused by bit line disturb during programming of other cells.
Solution Approach 2:
The second transistor acts as an intermediary device that performs read operations independently from the first transistor's programming operations. This intermediary structure allows the read function to be isolated from the disturb effects generated during programming, thereby improving reliability without requiring complex disturbance compensation circuitry.
2Reliability
If inhibit voltage is increased to reduce bit line disturb, then threshold voltage shifts are reduced, but programming operation complexity increases
Solution Approach 1:
By segmenting the memory cell into two separate transistors with distinct functions, the programming operation on the first transistor does not require complex voltage control to prevent disturb effects. The second transistor handles reads separately, simplifying the programming operation while maintaining data retention through reduced bit line disturb.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces bit line disturb and inhibit disturb effects, enhancing the data retention and endurance of non-volatile memory cells by equalizing the threshold voltage shifts, thus improving the reliability and longevity of the memory device.
Implementation Method 1
SONOS devices trap charge in a dielectric layer. SONOS transistors are programmed and erased using a quantum mechanical effect known as uniform channel, modified Fowler-Nordheim tunneling.
Implementation Method 2
A positive gate-to-substrate voltage causes electrons to tunnel from the channel to a charge-trapping dielectric layer and a negative gate-to-channel voltage causes holes to tunnel from the channel to the charge-trapping dielectric layer.
Data Source
AI summary
A method and device for trading off inhibit disturb against bit-line disturb in a non-volatile memory where a threshold shift per inhibit disturb is increased, a threshold shift per bit-line disturb is decreased and the total threshold shift over the expected lifetime of the non-volatile memory due to inhibit disturbs is approximately equalized with the total threshold shift over the expected lifetime of the non-volatile memory due to bit-line disturbs.