SONOS NAND Flash Erase Algorithm Using Periodic Voltage Pulses
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Solution Overview
Problem
Dielectric charge trapping memory cells face issues with erase saturation and high erase threshold voltages, limiting their performance and density in flash memory applications, especially in NAND arrays, due to the interference between charge storage layers and the need for slower erase speeds at lower voltages.
Innovation Solution
A method involving a sequence of voltages applied to the gate and substrate of dielectric charge trapping memory cells, where an initial high voltage creates a strong electric field for fast erase speed and subsequent lower voltages reduce the electric field to avoid saturation, allowing for quicker erasure while maintaining lower threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional biasing techniques are used to achieve lower erase threshold voltage, then the erase threshold voltage is reduced, but the erase speed becomes slower
Solution Approach 1:
The patent applies periodic action by using a sequence of voltage pulses with alternating polarities. The erase operation uses multiple voltage pulses: a first pulse with a first polarity to initiate electron injection, followed by a second pulse with a second polarity to extract electrons. This periodic voltage application enables controlled electron injection and extraction, achieving lower erase threshold voltages while maintaining practical erase speeds through the time-dependent nature of the pulsed operation.
2Speed
If high voltage is applied to achieve fast erase speed, then the erase speed increases, but erase saturation occurs limiting the minimum threshold voltage
Solution Approach 1:
The periodic action principle resolves this contradiction by using alternating voltage pulses. The first pulse injects electrons rapidly (achieving fast erase speed), while the second pulse with opposite polarity extracts electrons to prevent saturation and achieve the desired minimum threshold voltage. This time-separated injection and extraction process allows the system to benefit from both high-speed electron injection and controlled threshold voltage reduction without the harmful effects of continuous high-voltage saturation.
Solution Approach 2:
The patent applies parameter changes by varying the voltage polarity and magnitude across different time intervals. The erase operation uses a first voltage parameter (positive polarity) for electron injection, then switches to a second voltage parameter (negative polarity) for electron extraction. This dynamic parameter adjustment allows the system to achieve fast erase speeds during the injection phase while preventing saturation during the extraction phase, thereby achieving both high speed and low minimum threshold voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster erase speeds while preventing erase saturation, allowing for lower threshold voltages and improved memory cell performance by adjusting the voltage sequence and duration to efficiently reduce the threshold voltage of dielectric charge trapping memory cells.
Implementation Method 1
SONOS-type devices can be programmed by tunneling of electrons into the charge storage layer using one of a number of well-known biasing techniques (for example, Fowler Nordheim (FN) tunneling, Channel Hot Electron (CHE), etc)
Implementation Method 2
SONOS-type devices can be erased by hole tunneling into the charge storage layer or by electron de-trapping from the charge storage layer
Data Source
AI summary
A method for operating a dielectric charge trapping memory cell as described herein includes applying an initial voltage from the gate to the substrate of the memory cell for a predetermined period of time to reduce the threshold voltage of the memory cell. The method includes applying a sequence of voltages from the gate to the substrate of the memory cell to further reduce the threshold voltage of the memory cell, wherein a subsequent voltage in the sequence of voltages has a lower magnitude from the gate to the substrate than that of a preceding voltage in the sequence of voltages.