SONOS Memory Cell Fabrication via U-Shaped ONO Etching
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Solution Overview
Problem
Conventional methods for fabricating silicon-oxide-nitride-silicon (SONOS) non-volatile memory cells face issues such as nitride residue and silicon pitting due to improper hard mask coverage during the definition of tunnel regions, leading to non-uniform doping and performance limitations.
Innovation Solution
A multi-etching method is employed to define the tunnel region of the control gate, involving the formation of a pad oxide pattern, sequential ONO structures, and controlled etching steps to create a U-shaped and subsequently -shaped ONO structure, followed by gate structure formation, which addresses the issues of nitride residue and silicon pitting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a hard mask is formed to cover the tunnel region, then the tunnel region can be defined, but it leads to nitride residue being formed if the hard mask covers outside the tunnel region and results in non-uniformity of sequentially performed doping process
Solution Approach 1:
The patent segments the etching process into multiple distinct steps: a first etching step to remove oxide layer and form U-shaped structure, and a second etching step to remove nitride layer and form -shaped structure. This segmentation allows precise control over which materials are removed at each stage, preventing nitride residue while accurately defining the tunnel region.
Solution Approach 2:
The patent performs preliminary actions by first forming the U-shaped ONO structure through the first etching step before proceeding to the second etching step. This preliminary removal of the oxide layer creates a controlled environment that prevents subsequent nitride residue formation during tunnel region definition.
2Object-generated harmful factors
If a hard mask is formed to cover only the tunnel region, then nitride residue is avoided, but it leads to underlying silicon pitting by the following etching process
Solution Approach 1:
The patent segments the protective structure formation into two phases: first creating a U-shaped ONO structure that protects during initial etching, then transitioning to a -shaped structure that provides precise protection during subsequent etching steps. This segmented approach prevents silicon pitting while avoiding nitride residue.
Solution Approach 2:
The patent introduces an intermediary oxide layer that serves as a protective mediator during the etching process. This oxide layer is selectively removed in the first etching step to form the U-shaped structure, then partially removed in the second step to form the -shaped structure, providing controlled protection that prevents silicon pitting without causing nitride residue.
3Device complexity
If conventional single etching step is used, then process complexity is reduced, but manufacturing precision and performance are limited
Solution Approach 1:
The patent divides the etching process into two distinct segments with different objectives: the first etching step removes the oxide layer to form the U-shaped ONO structure, while the second etching step removes the nitride layer to form the -shaped structure and precisely define the tunnel region. This segmentation achieves high manufacturing precision despite increased process complexity.
Solution Approach 2:
The patent changes etching parameters between steps, using different etching chemistries and conditions for the first and second etching steps. This allows selective removal of different materials (oxide vs. nitride) with appropriate selectivity ratios, achieving precise tunnel region definition that cannot be obtained with a single etching step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the uniformity and performance of SONOS memory cells by reducing nitride residue and silicon pitting, enhancing product yields without significantly increasing manufacturing costs, and can be integrated into existing processes.
Implementation Method 1
removing a part of the first ONO structure exposed by the photoresist to form an U-shaped ONO structure
Implementation Method 2
the step (S6) is to dry etch the part of the U-shaped ONO structure in order to remove a part of the U-shaped ONO structure on the peripheral region of the pad oxide pattern
Data Source
AI summary
The invention provides a method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, comprising: (S1) forming a pad oxide pattern on a silicon substrate having a recess exposing a tunnel region of the silicon substrate; (S2) forming a bottom oxide layer, a nitride layer, a top oxide layer covering the recess and the pad oxide pattern to form a first ONO structure; (S3) forming a photoresist on the first ONO structure covering the recess and a peripheral region of the pad oxide pattern; (S4) removing a part of the first ONO structure exposed by the photoresist to form an U-shaped ONO structure; (S5) trimming the photoresist to exposed a part of the U-shaped ONO structure above the recess; (S6) removing the part of the U-shaped ONO structure; (S7) removing the photoresist; (S8) removing the pad oxide pattern and the top oxide layer; and (S9) forming a gate structure.