Per-Pixel Detector Bias Control via SONOS Injection Transistor
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Solution Overview
Problem
Legacy infrared imagers face performance and yield issues due to detector bias non-uniformity, leading to unusable pixels and reduced imaging array performance, as a universal gate bias voltage can result in excessive 'dark current' or insufficient bias voltage across the array.
Innovation Solution
The implementation of a silicon-oxide-nitride-oxide-silicon (SONOS) FET as an injection transistor, allowing for individual programming of each pixel's detector bias voltage by setting the SONOS gate voltage, which is stored in a silicon nitride layer, to ensure optimal operation of each photodiode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a universal gate bias voltage is applied to all pixels, then the circuit design is simple, but detector bias non-uniformity causes excessive dark current or insufficient bias voltage in some pixels
Solution Approach 1:
The patent applies local quality by providing each pixel with an individually controllable gate bias voltage through a programmable voltage source. This allows each pixel to have customized bias settings tailored to its specific detector characteristics, resolving the non-uniformity issue while maintaining manufacturing simplicity through integrated circuit implementation.
Solution Approach 2:
The patent implements dynamics by making the gate bias voltage programmable and adjustable for each pixel. The voltage can be dynamically set during or after manufacturing to compensate for detector variations, allowing the system to adapt to individual pixel requirements rather than using a fixed universal bias voltage.
2Reliability
If individual bias control is implemented for each pixel, then detector bias uniformity is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by using a single programmable voltage source that can serve multiple pixels simultaneously. The same hardware infrastructure is used to provide individualized bias control to many pixels, reducing the overall complexity compared to having separate control circuits for each pixel while still achieving individualized bias settings.
Solution Approach 2:
The patent merges the bias control functionality into the pixel circuit itself by integrating the programmable voltage source directly with the detector and readout circuitry. This consolidation eliminates the need for external bias control equipment and reduces the number of discrete components, thereby managing device complexity while achieving individual bias control.
3Power
If higher bias voltage is applied to increase photo-current, then signal strength is improved, but dark current also increases reducing signal-to-noise ratio
Solution Approach 1:
The patent applies parameter changes by allowing precise adjustment of the gate bias voltage for each pixel to find the optimal operating point. By programmatically setting the bias voltage, the system can maximize photo-current signal strength while keeping dark current at acceptable levels, achieving the best signal-to-noise ratio for each individual pixel's characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables each pixel to operate within a usable range, alleviating issues of detector and transistor non-uniformity, thereby improving the overall imaging performance and yield by allowing for tailored bias voltage settings across the array.
Implementation Method 1
the gate is formed of a gate stack that includes a layer of silicon nitride that stores current to set the SONOS gate voltage
Implementation Method 2
a photo-diode, an integration capacitor arranged to receive a photo current from the photo-diode and to store charge developed from the photo current
Data Source
AI summary
A pixel includes a photo-diode, an integration capacitor arranged to receive a photo current from the photo-diode and to store charge developed from the photo current; and an injection transistor disposed between the photo-diode and the integration capacitor that controls flow of the photo current from the photo-diode to the integration capacitor, the injection transistor having a gate, a source electrically coupled to the photo-diode at a first node, and a drain electrically coupled to the integration capacitor. The injection transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) FET having its gate set to a SONOS gate voltage to control a detector bias voltage of the photo-diode at the first node.