SONOS Memory Cell Pulse Shaping for Endurance
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Solution Overview
Problem
SONOS memory cells face endurance degradation after approximately 10K cycles, making it difficult to achieve 100K/1M cycle specifications in advanced technologies like 64 nm and 28 nm, due to damage from program/erase cycling, which affects data retention and threshold voltage stability.
Innovation Solution
Implementing pulse shaping techniques for program/erase cycles, including control of pulse signals with four or more phases, such as ramped pulses, staircase signals, and multiple pulses, to reduce electric field stress and minimize damage to the charge trapping layers, allowing for controlled charge injection and removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional program/erase cycling is used in SONOS memory cells, then programming and erasing operations can be performed, but endurance degrades after about 10K cycles due to damage to the charge trapping layer
Solution Approach 1:
The patent applies periodic pulse shaping to the program/erase cycles, using multi-phase pulses with specific timing characteristics. The pulse signal includes a first phase with a first amplitude and duration, a second phase with a second amplitude and duration, and a third phase with a third amplitude and duration. This periodic structured action reduces damage to the charge trapping layer while maintaining effective programming and erasing operations, enabling endurance beyond 10K cycles.
2Reliability
If standard pulse signals are used for programming and erasing, then memory operations are simple and fast, but the threshold voltage window degrades and data retention performance deteriorates after repeated cycling
Solution Approach 1:
The patent segments the program/erase pulse signal into multiple distinct phases, where each phase has specific amplitude and duration characteristics optimized for different aspects of the memory operation. The pulse signal is divided into a first phase, second phase, and third phase, allowing precise control over charge injection and removal processes. This segmentation maintains data retention performance by preventing threshold voltage window degradation while managing the complexity through structured phase definitions.
3Productivity
If higher programming voltages are applied to improve write speed, then programming efficiency increases, but damage to the ONO stack increases, reducing endurance
Solution Approach 1:
The patent dynamically changes voltage parameters across different phases of the pulse signal. The first phase uses a first amplitude, the second phase uses a second amplitude, and the third phase uses a third amplitude. This parameter variation allows efficient charge injection during high-voltage phases while using lower voltages during other phases to minimize damage to the oxide-nitride-oxide stack. The result is improved programming speed without sacrificing endurance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The pulse shaping techniques improve endurance and data retention characteristics, enabling SONOS memory cells to withstand 100K/1M cycles by reducing damage and maintaining a stable threshold voltage window, similar to uncycled devices, thus extending the memory cell's lifespan and performance.
Implementation Method 1
a pulse signal with four or more phases is applied to control the write cycle
Data Source
AI summary
Apparatuses and methods of pulse shaping a pulse signal for programming and erasing a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory cell are described. In one method a pulse shape of a pulse signal is controlled to include four or more phases for programming or erasing a SONOS memory cell. A write cycle is performed to program or erase the SONOS memory with the pulse signal with the four or more phases.