High Voltage Tolerant Row Driver for SONOS Memory
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Solution Overview
Problem
The scaling down of SONOS devices for smaller and faster non-volatile memory devices poses challenges due to high voltage signals causing stress on thinner gate oxides, which can be mitigated but at the cost of increased complexity and expense by adding additional devices.
Innovation Solution
A row driver circuit is designed to generate additional bias voltages for p- and n-wells of transistors, employing extended drain devices and multiple levels of encoding for high voltage signals, allowing for efficient operation in high voltage modes while reducing electric field stress on gate oxides, and using cascoded devices to protect against overvoltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage signals are used to erase and write data to SONOS memory cells, then data storage functionality is achieved, but stress on thinner gate oxides increases causing device reliability degradation
Solution Approach 1:
The patent introduces a row driver circuit as an intermediary component between the high voltage signals and the SONOS memory cells. This driver circuit generates and controls the high voltage signals (VPOS and VNEG) to be applied to the word lines, thereby mediating the stress on the gate oxide by precisely controlling when and how these voltages are applied during program and erase operations
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting voltage levels and timing sequences during different operation modes (program, erase, read). The row driver circuit changes voltage parameters (VPOS, VNEG, VREAD) and their application timing to achieve reliable data storage while minimizing unnecessary stress on the gate oxide during non-critical operations
2Reliability
If additional devices are employed to mitigate high voltage stress on thinner gate oxides, then device reliability is improved, but circuit complexity and manufacturing cost increase
Solution Approach 1:
The row driver circuit is designed to perform multiple functions: generating high voltage signals, controlling word line selection, managing different operation modes (program, erase, read), and protecting the gate oxide. By consolidating these functions into a single multi-functional circuit rather than adding separate protective devices for each function, the patent improves reliability without proportionally increasing circuit complexity
Solution Approach 2:
The patent merges the functions of high voltage generation, word line control, and gate oxide protection into a single integrated row driver circuit. This consolidation eliminates the need for multiple separate protective devices and control circuits, thereby improving reliability through comprehensive protection while keeping the overall circuit complexity manageable through functional integration
Data Source
AI summary
A circuit is configured to supply a first gate voltage (PG1) at a first voltage bias (VP1) to a source of a first transistor providing an output (WLS), providing the first voltage bias (VP1) to a second transistor and supplying a second voltage bias (VN1) and a second gate voltage (NG1) to a third transistor, the second transistor coupled in series to the third transistor and in parallel with the first transistor, to supply a third voltage bias (VP2) and a third gate voltage (PG2) to a fourth transistor, and a fourth voltage bias (VN2) and a fourth gate voltage (NG2) to a fifth transistor, the fourth transistor coupled in series to the fifth transistor, and the fourth and fifth transistors coupled to a gate of the second transistor, and to provide a fifth voltage bias (VN3) to a line connecting the third transistor to the fifth transistor.