SONOS Charge Trap Memory With Segmented Blocking Dielectric
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Solution Overview
Problem
SONOS-type transistors face limitations in program and erase windows, leading to restricted performance due to limited back-streaming of electrons and poor data retention in the charge-trapping layer, which affects the scalability and efficiency of nonvolatile charge trap memory devices.
Innovation Solution
Incorporating a high dielectric constant blocking region and a multi-layer or graded blocking dielectric layer to mitigate back-streaming and enhance data retention, along with the use of decoupled plasma nitridation processes and deuterated layers to improve the charge-trapping efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SONOS transistor structure is used, then device simplicity is maintained, but program and erase windows are limited and data retention is poor
Solution Approach 1:
The blocking dielectric layer is divided into multiple sub-layers (first blocking dielectric sub-layer, second blocking dielectric sub-layer, third blocking dielectric sub-layer) with different dielectric constants. This segmentation allows each sub-layer to contribute differently to charge blocking, improving overall data retention while managing the complexity through a systematic multi-layer approach
Solution Approach 2:
Different regions of the blocking dielectric layer are assigned different dielectric constants (K1, K2, K3) to optimize local charge blocking properties. The first sub-layer has dielectric constant K1, the second has K2, and the third has K3, where these values are specifically chosen to enhance electron back-streaming prevention in critical regions while maintaining overall device performance
2Reliability
If single-layer blocking dielectric is used, then manufacturing process is simple, but electron back-streaming is not effectively mitigated
Solution Approach 1:
The blocking dielectric layer is segmented into three distinct sub-layers deposited sequentially through multiple fabrication steps. This segmentation enables effective mitigation of electron back-streaming by creating a gradient structure that progressively blocks electrons at different energy levels, while the systematic deposition process manages manufacturing complexity
Solution Approach 2:
The blocking dielectric layer is constructed as a composite structure with multiple materials or compositions having different dielectric constants. This composite approach effectively mitigates electron back-streaming by creating multiple barriers with varying properties, while the use of standard deposition techniques for each layer maintains reasonable ease of manufacture
3Reliability
If conventional charge-trapping layer is used, then device structure is simple, but charge-trapping efficiency is insufficient
Solution Approach 1:
The charge-trapping layer is formed as a composite nitride layer with specific composition and structure that enhances charge-trapping efficiency. This composite structure allows for improved reliability in charge retention while managing device complexity through a well-defined layer architecture
Solution Approach 2:
The nitride charge-trapping layer is positioned and structured to optimize local charge-trapping properties at the interface with the tunnel dielectric and blocking dielectric layers. This local optimization enhances overall charge-trapping efficiency while maintaining a manageable layer structure
4Speed
If thinner tunnel dielectric is used, then program speed is improved, but data retention deteriorates
Solution Approach 1:
The blocking dielectric layer is segmented into multiple sub-layers with different dielectric constants, where the first sub-layer (with dielectric constant K1) is positioned adjacent to the tunnel dielectric. This segmentation allows the thinner tunnel dielectric to enable fast programming while the multi-layer blocking structure compensates for data retention through progressive electron blocking at different interfaces
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The high dielectric constant blocking region and advanced layer structures enable deeper erase and greater program/erase window differentials, improving device performance and data retention, while the decoupled plasma and deuterated layers enhance the charge-trapping capabilities, addressing the limitations of conventional SONOS transistors.
Implementation Method 1
the charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias
Implementation Method 2
the charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process
Data Source
AI summary
A method includes forming a first oxide layer. The method further includes etching a portion of the first oxide layer using a first decoupled plasma nitridation process. The method includes forming, subsequent to the etching, a charge-trapping layer on the first oxide layer.