Strain Inducing Structure for SONOS Memory Data Retention
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Solution Overview
Problem
Current non-volatile semiconductor memories face challenges in data retention time, scalability, and compatibility with logic transistors, as well as inefficiencies in programming speed and power usage, particularly in smaller geometries and System-On-Chip applications.
Innovation Solution
The implementation of a strain inducing structure over non-volatile memory transistors, such as a silicon-oxide-nitride-oxide-silicon (SONOS) transistor, using techniques like High Aspect Ratio Process (HARP) oxidation and plasma enhanced chemical vapor deposition (PECVD) to increase charge retention and induce strain in both memory and logic transistors, improving data retention and programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If band-gap engineering is used to improve data retention, then charge trapping and leakage current reduction are improved, but manufacturing precision and control of charge storage and insulating layers become increasingly difficult at smaller geometries
Solution Approach 1:
The patent changes the physical state and properties of the semiconductor channel by introducing strain through silicon-germanium source/drain structures. This strain modifies the band structure and carrier mobility parameters, improving charge trapping efficiency and data retention without requiring precise control of charge storage layer composition and thickness at scaled geometries
Solution Approach 2:
The patent replaces the chemical/compositional approach of band-gap engineering with a mechanical strain approach. By introducing physical strain through misfit dislocations in silicon-germanium structures, the patent achieves improved charge retention without relying on precise compositional control of insulating and charge storage layers
2Reliability
If band-gap engineering processes are implemented to improve memory transistor performance, then data retention is improved, but compatibility with logic transistor fabrication processes is reduced
Solution Approach 1:
The patent implements a universal strain induction approach using silicon-germanium source/drain structures that can be applied to both memory transistors and logic transistors on the same substrate. This single process provides multi-functionality, improving both data retention in memory devices and carrier mobility in logic devices without requiring separate fabrication streams
Solution Approach 2:
The patent uses strain as a universal parameter that can be induced in both memory and logic transistors through the same silicon-germanium fabrication process. This parameter change approach is compatible with standard CMOS logic fabrication, enabling co-fabrication of memory and logic devices on a common substrate
3Ease of manufacture
If conventional memory transistor structures are used, then fabrication is simpler, but programming speed and efficiency are reduced
Solution Approach 1:
The patent modifies the carrier mobility parameter in the channel region through strain induction from silicon-germanium source/drain structures. This parameter change increases the speed at which carriers can be injected into and extracted from the charge storage layer, thereby improving programming and erasing speeds while maintaining fabrication compatibility
Solution Approach 2:
The patent uses composite silicon-germanium structures combining silicon and germanium in specific ratios to create source/drain regions that induce controlled strain in the channel. This composite material approach improves programming efficiency through enhanced carrier mobility while using standard semiconductor fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data retention by up to an order of magnitude and increases programming speed, while being compatible with standard logic transistor fabrication processes, making it suitable for embedded memory and System-On-Chip applications.
Implementation Method 1
forming a strain inducing structure over the gate of the non-volatile memory transistor to increase charge retention of the charge trapping layer
Implementation Method 2
using techniques like High Aspect Ratio Process (HARP) oxidation
Implementation Method 3
plasma enhanced chemical vapor deposition (PECVD) to increase charge retention
Data Source
AI summary
Non-volatile semiconductor memories and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the method includes: (i) forming a gate for a non-volatile memory transistor on a surface of a substrate overlaying a channel region formed therein, the gate including a charge trapping layer; and (ii) forming a strain inducing structure over the gate of the non-volatile memory transistor to increase charge retention of the charge trapping layer. Preferably, the memory transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) transistor comprising a SONOS gate stack. More preferably, the memory also includes a logic transistor on the substrate, and the step of forming a strain inducing structure comprises the step of forming the strain inducing structure over the logic transistor. Other embodiments are also disclosed.