Threshold Voltage Switching Insulation Layer for SONOS Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional nonvolatile memory devices face challenges in achieving high program speed with low power consumption while maintaining reliable data retention, due to issues with leakage current, direct tunneling, and increased power consumption associated with high operation voltages in SONOS structures.
Innovation Solution
A nonvolatile memory device utilizing a threshold voltage switching material for the second insulation layer, which changes to a low resistance state only when a voltage greater than a threshold voltage is applied, allowing for efficient charge trapping and storage without the need for additional voltage pulses to maintain the program state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the thickness of the silicon oxide film is reduced to enhance operation speed, then operation speed is improved, but data retention characteristic deteriorates due to increase of direct tunneling and stress induced leakage current
Solution Approach 1:
The patent divides the single-layer silicon oxide film into a multi-layer structure consisting of a first insulation layer (thickness: 5-15 nm) and a second insulation layer (thickness: 15-30 nm). This segmentation allows the first layer to provide sufficient thickness for data retention while the overall structure enables faster operation, resolving the contradiction between speed and reliability.
2Productivity
If the program voltage is increased to enhance program speed, then program speed is improved, but power consumption increases and defects inside the tunneling oxide film increase
Solution Approach 1:
The patent changes the physical parameters of the insulation structure by introducing a multi-layer configuration with different thicknesses and material compositions. This allows program operation at reduced voltages (lower power consumption) while maintaining fast program speeds, as the optimized structure enables efficient charge injection without requiring excessive voltage.
3Productivity
If the thickness of the tunneling oxide film is reduced for enhanced program speed while program voltage is constantly maintained, then program speed is improved, but leakage current occurs and reliability deteriorates
Solution Approach 1:
By segmenting the oxide film into multiple layers with optimized thicknesses, the patent achieves fast program speed without excessive thinning. The first insulation layer (5-15 nm) is thick enough to prevent leakage current while the overall structure enables rapid charging, resolving the contradiction between program speed and leakage current suppression.
4Ease of operation
If a blocking insulation layer formed of a silicon oxide film is used for erasing operation, then erasing operation is enabled, but electrons may be injected into a nitride film from a gate due to increase of an erasing voltage, causing imperfect erasing
Solution Approach 1:
The patent employs a composite insulation structure with a first insulation layer and a second insulation layer having different properties. This composite structure enables effective erasing operation while preventing electron injection into the nitride film, ensuring complete erasure without compromising reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables fast programming and improved data retention for at least 10 years by eliminating tunneling and reducing power consumption, while maintaining reliability and operation speed.
Implementation Method 1
a second insulation layer formed on the charge trap layer, and having a state change between a low resistance state and a high resistance state according to an applied voltage pulse
Implementation Method 2
The charge trap layer may perform a program operation by trapping therein charges introduced from the second insulation layer
Implementation Method 3
The second insulation layer may prevent charges trapped in the charge trap layer, from being discharged to the gate electrode layer, in a high resistance state
Data Source
AI summary
The present invention relates to a nonvolatile memory device and to a method for manufacturing same. According to the present invention, the blocking insulation layer of a nonvolatile memory device having a typical SONOS structure is replaced with a threshold voltage switching material, which changes to a low resistance state only while a voltage greater than a threshold voltage is applied while maintaining a high resistance state under normal conditions and returning to the high resistance state when the applied voltage is removed. The present invention performs a program operation by injecting charges from a gate electrode layer into a charge trap layer through an insulation layer formed of the threshold voltage switching material after applying a voltage pulse greater than the threshold voltage to the gate electrode layer.