SONOS Transistor Barrier Wall Gate Integration
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in reducing the critical dimension of transistors with SONOS structures, as the distance between select and memory gates is large, making it difficult to achieve smaller dimensions and adapt to different work requirements.
Innovation Solution
A manufacturing method for transistors with an SONOS structure that involves depositing oxide and ONO layers, forming a barrier wall to separate the select and memory gates, and using polycrystalline silicon to create symmetrical gates, allowing for a simpler process to reduce the distance between gates and minimize transistor volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a conventional memory cell structure with separate select and memory gates is used, then the transistor can function as a memory cell, but the distance between gates is large resulting in increased device volume
Solution Approach 1:
The patent merges the select gate and memory gate into a single continuous gate structure, eliminating the gap between them. This is achieved by forming one gate electrode that spans both the select transistor region and the memory transistor region, thereby reducing the overall device volume while maintaining the functional separation through different gate electrode portions.
Solution Approach 2:
The unified gate structure is segmented into functionally distinct portions: a first gate electrode portion for the select transistor and a second gate electrode portion for the memory transistor. This segmentation allows each portion to be independently controlled with separate control signals, preserving the operational independence of select and memory functions while achieving physical integration.
2Length of moving object
If the distance between select gate and memory gate is reduced, then transistor dimension decreases, but electrical isolation between gates becomes more challenging
Solution Approach 1:
The gate structure employs local quality differentiation by having distinct portions with different electrical characteristics. The first gate electrode portion is configured for the select transistor with specific electrical properties, while the second gate electrode portion is configured for the memory transistor with different electrical properties. This allows each region to be optimized for its specific function while maintaining close proximity.
Solution Approach 2:
The continuous gate structure acts as an intermediary that provides both electrical connection and isolation. By using a single gate electrode material and structure that spans both regions, the patent achieves electrical isolation between select and memory functions while maintaining physical continuity, with the isolation achieved through controlled electrical properties rather than physical separation.
3Device complexity
If a simpler manufacturing process is used, then device complexity decreases, but achieving precise gate alignment and symmetry becomes difficult
Solution Approach 1:
The single continuous gate structure serves multiple functions simultaneously: it acts as the gate for the select transistor in one region and the gate for the memory transistor in another region. This universal gate structure eliminates the need for separate gate formation processes, simplifying manufacturing while ensuring precise alignment through a single formation step. The symmetrical configuration is achieved inherently through the unified structure design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of smallest memory cells with reduced transistor dimensions, improving adaptability and operational efficiency by using existing tools and photomasks, while ensuring electrical separation and meeting operating voltage requirements.
Implementation Method 1
a barrier wall structure is formed on upper surfaces of adjacent portions of the oxide layer and the ONO memory layer to isolate the select gate and the memory gate from each other
Implementation Method 2
depositing an oxide layer on an upper surface of the select transistor well, depositing an ONO memory layer on an upper surface of the memory transistor well
Data Source
AI summary
The present disclosure provides a manufacturing method for a transistor with an SONOS structure, including providing a semiconductor substrate, wherein the semiconductor substrate includes a select transistor well and a memory transistor well; depositing an oxide layer on an upper surface of the select transistor well, depositing an ONO memory layer on an upper surface of the memory transistor well, depositing a barrier wall over adjacent portions of the select transistor well and the memory transistor well, depositing polycrystalline silicon covering the oxide layer, the ONO memory layer, and the barrier wall, and etching the polycrystalline silicon, to retain the polycrystalline silicon deposited on both sides of the barrier wall so as to form a select gate and a memory gate, and removing the oxide layer and the ONO layer on a surface of the semiconductor substrate other than the select gate, the barrier wall, and the memory gate.