SONOS Memory Cell Spacing via Wet Etching ONO Patterning
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Solution Overview
Problem
Conventional SONOS non-volatile memory cell manufacturing techniques face challenges in reducing the distance between adjacent cells due to manufacturing process margins and the use of a pad oxide layer, which limits their application in advanced technology nodes.
Innovation Solution
A method involving wet etching processes to form an ONO structure without a pad oxide layer, where a higher-density second oxide layer is used to define the nitride pattern, allowing for reduced cell spacing and improved device integrity by eliminating the pad oxide layer overlap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a pad oxide layer is used during dry etching process to protect the substrate, then the substrate is protected from damage, but the overlap region between the pad oxide layer and the ONO multilayered structure increases the distance between adjacent SONOS non-volatile memory cells
Solution Approach 1:
The invention extracts and removes the pad oxide layer from the manufacturing process. By using wet etching processes instead of dry etching, the need for a pad oxide layer is eliminated, thereby removing the source of the overlap region that increased cell spacing. This allows the ONO structure to be directly formed over the substrate without requiring additional protective layers.
Solution Approach 2:
The invention substitutes the dry etching process with wet etching processes. This process substitution eliminates the need for a pad oxide layer, as wet etching can be performed without requiring such protective structures. The replacement of the mechanical/physical dry etching process with chemical wet etching processes resolves the contradiction by removing the overlapping region while still achieving the desired patterning.
2Reliability
If dimension tolerance is reserved for manufacturing process margin, then manufacturing reliability is improved, but the distance between two adjacent SONOS non-volatile memory cells cannot be reduced
Solution Approach 1:
The invention changes the etching process parameters by transitioning from dry etching to wet etching. This parameter change in the manufacturing process enables tighter dimensional control and reduces the need for excessive dimension tolerance reserves. The wet etching process provides better process margins that allow for reduced cell spacing while maintaining manufacturing reliability.
3Reliability
If the ONO multilayered structure is defined by dry etching process with pad oxide layer overlap, then the structure is protected during etching, but it becomes difficult to reduce the distance between two adjacent SONOS non-volatile memory cells
Solution Approach 1:
The invention extracts and eliminates the pad oxide layer from the process flow. By removing this protective layer that caused overlap regions, the distance between adjacent memory cells can be reduced. The wet etching process provides alternative protection mechanisms that do not require the pad oxide layer, thereby resolving the contradiction between structure protection and cell spacing reduction.
Solution Approach 2:
The invention substitutes the dry etching process with wet etching processes for defining the ONO multilayered structure. This substitution eliminates the need for pad oxide layer protection during etching, as wet etching can be performed with different protection strategies that do not create overlapping regions. This process change enables reduced cell spacing while maintaining structure integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a reduction in the distance between SONOS non-volatile memory cells, enhancing device integrity and enabling more compact designs suitable for advanced technology nodes.
Implementation Method 1
A first wet etching process is then performed to remove the second oxide layer exposed by the first photoresist pattern so as to form an oxide hard mask
Implementation Method 2
a second wet etching process is performed to remove the nitride layer exposed by the oxide hard mask so as to form a nitride pattern
Data Source
AI summary
A method for manufacturing a silicon-oxide-nitride-oxide-silicon non-volatile memory cell includes following steps. An implant region is formed in a substrate. A first oxide layer, a nitride layer, and a second oxide layer are formed and stacked on the substrate. A density of the second oxide layer is higher than a density of the first oxide layer. A first photoresist pattern is formed on the second oxide layer and corresponding to the implant region. A first wet etching process is then performed to form an oxide hard mask. A second wet etching process is performed to remove the nitride layer exposed by the oxide hard mask to form a nitride pattern. A cleaning process is then performed to remove the oxide hard mask and the first oxide layer exposed by the nitride pattern, and a gate oxide layer is then formed on the nitride pattern.