SONS Synaptic Structure for CMOS-Compatible Plasticity Control

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing synaptic devices fail to accurately imitate various synaptic behaviors of biological synapses and have poor compatibility with CMOS technology, limiting their effectiveness in neuromorphic computing systems.

Innovation Solution

A synaptic device with a SONS structure, comprising a doped poly-silicon/blocking oxide/charge trap nitride/silicon channel, where the gate electrode is made of silicon, the blocking insulating layer of oxide, and the charge trap layer of nitride, allowing for control of post-synaptic current and synaptic plasticity through gate voltage pulses, exhibiting characteristics like biological synapses such as spike amplitude, duration, frequency, number, and timing dependent plasticity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing synaptic devices are used, then device structure is simple, but they fail to accurately imitate biological synaptic behaviors and have poor CMOS compatibility

Engineering Contradiction:

Improveimitation accuracy of biological synaptic behaviorsVSAvoiddevice structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The device is segmented into distinct functional layers: channel layer, charge trap layer, and blocking insulating layer. Each layer performs a specific function - the channel layer conducts current, the charge trap layer stores charges to modulate conductivity, and the blocking insulating layer prevents charge leakage. This segmentation enables accurate imitation of biological synaptic behaviors while maintaining manufacturability through standardized CMOS processes.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The synaptic device employs a composite structure combining organic and inorganic materials. The channel layer uses organic semiconductor materials that exhibit field-effect transistors behavior, while the charge trap and blocking insulating layers use inorganic materials. This composite approach enables both accurate biological synaptic imitation and compatibility with CMOS technology.

Inventive Principle:

Principle #40Composite materials

2Ease of manufacture

If existing synaptic devices are used, then manufacturing process is simple, but they have poor compatibility with CMOS technology

Engineering Contradiction:

ImproveCMOS compatibilityVSAvoidsynaptic behavior simulation capability

Core Design Contradiction:

Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The device structure parameters are optimized to achieve both CMOS compatibility and accurate synaptic behavior. The thickness of the channel layer (5-50 nm), charge trap layer (2-20 nm), and blocking insulating layer (2-20 nm) are specifically controlled. These parameter changes enable the device to function accurately as a synaptic device while being manufacturable using standard CMOS processes.

Inventive Principle:

Principle #35Parameter changes

3Manufacturing precision

If charge trap layer is directly contacting the channel, then synaptic plasticity control is improved, but charge leakage may increase

Engineering Contradiction:

Improvesynaptic plasticity control precisionVSAvoidcharge leakage

Core Design Contradiction:

Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The blocking insulating layer serves as an intermediary between the charge trap layer and the external environment. It prevents charge leakage while allowing the charge trap layer to effectively modulate the channel conductivity. This intermediary layer resolves the contradiction by enabling precise synaptic plasticity control through charge trapping without suffering from charge leakage issues.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The synaptic device effectively simulates biological synaptic behaviors and is fully compatible with CMOS technology, enabling efficient control of synaptic plasticity and integration into neuromorphic devices and neural networks.

Implementation Method 1

charges trapped in the charge trap layer by the application of the gate voltage

Methodology Applied

Scientific EffectCharge trapping:

Implementation Method 2

charges trapped in the charge trap layer by the application of the gate voltage are diffused and outflowed to the channel over time

Methodology Applied

Scientific EffectDiffusion: Diffusion

Data Source

PatentUS20230419089A1Synaptic device, neuromorphic device including synaptic device, and operating methods thereof

Publication Date: 2023.12.28 SK HYNIX INC

AI summary

A synaptic device, a neuromorphic device including the synaptic device, and operating methods thereof are disclosed. A synaptic device may comprise a channel, a charge trap layer directly contacting the channel, a blocking insulating layer disposed on the charge trap layer, a control electrode disposed on the blocking insulating layer, a first terminal connected to a first region of the channel, and a second terminal connected to a second region of the channel. The synaptic device may change a post-synaptic current (PSC) and control synaptic plasticity according to a control signal applied to the control electrode. The synaptic device may have a SONS (doped poly-silicon/blocking oxide/charge trap nitride/silicon channel) structure. The synaptic device may have SADP characteristics, SDDP characteristics, SFDP characteristics, SNDP characteristics, and STDP characteristics.