SoP with TSV Interposer and Micro Bump Memory
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Solution Overview
Problem
The manufacturing cost of system-in-package (SiP) with multiple DRAM chips becomes prohibitively expensive due to the need for through-silicon-vias (TSVs) in both the SoC and DRAM chips, requiring additional development and production of two different types of DRAM chips.
Innovation Solution
A system on package (SoP) configuration where the first package includes a SoC with through-vias and a memory device connected via micro bumps, and a second package with a memory controller and additional memory devices, electrically connected using stack connection solder balls, reducing the need for TSVs in the DRAM chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If through-silicon-vias (TSVs) are provided in both the SoC and DRAM chips to electrically connect multiple DRAM chips stacked on each other, then high memory capacity and bandwidth are achieved, but manufacturing cost becomes prohibitively high
Solution Approach 1:
The system divides the memory architecture into two segments: a first package containing DRAM chips with TSVs for high-speed access, and a second package containing DRAM chips with micro bumps for additional capacity. This segmentation allows the system to achieve high memory capacity while controlling manufacturing costs by not requiring TSVs in all memory chips.
Solution Approach 2:
The first PCB acts as an intermediary substrate that electrically connects the first package (with TSV-based DRAM chips) and the second package (with micro bump-based DRAM chips). This intermediary structure enables cost-effective integration of mixed TSV and micro bump technologies while maintaining high bandwidth and density.
2Ease of manufacture
If the topmost DRAM chip is provided with micro bumps instead of TSVs to reduce manufacturing cost, then manufacturing cost is reduced, but additional development costs are incurred due to needing to manufacture two different types of DRAM chips
Solution Approach 1:
The first PCB serves multiple functions: it provides electrical connections for both TSV-based and micro bump-based DRAM chips, acts as a mechanical support structure, and enables unified control of the mixed memory architecture. This multi-functionality reduces the need for separate development paths for different chip types.
Solution Approach 2:
The system uses micro bumps as a simplified copy or alternative to TSVs in the second package. Instead of developing entirely different chip architectures, the design replicates the basic DRAM chip structure but uses a different interconnection method (micro bumps versus TSVs), reducing development complexity while maintaining functionality.
3Quantity of substance
If multiple DRAM chips are stacked vertically to achieve high memory capacity, then memory density is improved, but the need for TSVs in all chips increases manufacturing complexity and cost
Solution Approach 1:
The system applies different interconnection qualities to different locations in the memory stack: the first package uses TSVs for high-speed, high-density connections where performance is critical, while the second package uses micro bumps for additional capacity where cost-effectiveness is prioritized. This local differentiation optimizes both density and complexity.
Solution Approach 2:
The invention transitions from a purely vertical stacking architecture (requiring TSVs through all chips) to a hybrid architecture that incorporates both vertical stacking and lateral expansion across two packages. This dimensional change allows the system to achieve high memory density while reducing the need for TSVs in every chip.
Data Source
AI summary
A system on package includes a first package and a second package stacked on the first package and electrically connected to one another through metal contacts. The first package includes a first printed circuit board (PCB), a system on chip which is connected to the first PCB through bumps, and a first memory device which is connected to the system on chip through micro bumps connected to vias in the system on chip. The second package includes a second PCB, a second memory device connected to the second PCB, a third memory device connected to the second PCB, and a memory controller which is connected to the second PCB and controls the third memory device.