Sorter Hardware Verification Using Extended Input Constraints
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Solution Overview
Problem
Conventional formal verification of sorters is complex and slow, especially for large multisets of inputs, due to the difficulty in verifying multiplicity and the potential for non-comprehensive testing to miss errors.
Innovation Solution
The method involves generating a modified version of the hardware design for the sorter that accepts extended inputs with additional unique bits, and performing formal verification by implementing constraints that ensure the least significant bits of each input represent a unique value, thereby simplifying the verification process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional formal verification is used to verify sorter properties, then verification completeness is improved, but verification time and computational complexity increase significantly
Solution Approach 1:
The patent segments the verification process by dividing the set of all possible inputs into multiple subsets. Instead of verifying all inputs simultaneously, the verification is performed on each subset separately. This segmentation reduces the computational complexity and verification time while maintaining completeness, as each subset can be verified independently and more efficiently
Solution Approach 2:
The patent applies preliminary action by performing a coarse verification first to identify which subsets of inputs require detailed verification. The input space is preprocessed and organized into subsets based on certain criteria, allowing the formal verification tool to focus computational resources only on the relevant subsets rather than exhaustively verifying all possible inputs from the beginning
2Measurement precision
If the number of test vectors is increased to achieve comprehensive testing, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the large set of test vectors into multiple smaller subsets. Each subset contains a manageable number of test vectors that can be processed independently. This segmentation maintains testing comprehensiveness by ensuring all input combinations are covered across the subsets, while reducing the complexity of managing and processing the entire test vector set at once
Solution Approach 2:
The patent applies partial action by verifying properties on subsets of inputs rather than all possible inputs simultaneously. The input space is partially explored through multiple passes over different subsets, achieving comprehensive coverage through repeated partial verifications rather than a single exhaustive verification of all inputs
Data Source
AI summary
Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.