Comparator-Reuse Sorting Circuit for Scalable Median Filters
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Solution Overview
Problem
Hardware implementations of median filters require a large number of comparators, which consume significant die area and increase exponentially with the input window size, making median filtering unfeasible for some applications and leading to inferior performance when linear filters are used instead.
Innovation Solution
A sorting circuit that re-uses a single stage of comparators over multiple phases using multiplexors and a scheduling circuit to reduce the number of comparators and registers, allowing for efficient sorting and median filtering with a significantly reduced hardware requirement, where the number of comparators increases linearly with the input sequence values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sorting network with multiple stages of comparators is used to implement median filtering, then the filtering performance is improved, but the die area increases exponentially with the input window size
Solution Approach 1:
The sorting network is divided into multiple time phases where comparators are re-used periodically. Instead of having all comparators operate simultaneously, the system cycles through different comparison phases, re-using the same physical comparators at different times to perform different comparison tasks, thereby reducing the total number of comparators needed.
Solution Approach 2:
The system transitions from a static, simultaneous comparison architecture to a dynamic, time-multiplexed architecture. Multiplexors dynamically route data between comparators across different phases, and the scheduling circuit dynamically controls which comparisons occur at each phase, enabling the same hardware to adapt its function over time.
2Productivity
If multiple stages of comparators are used for sorting, then the sorting capability is improved, but the number of comparators increases exponentially
Solution Approach 1:
Each comparator is designed to be multi-functional, serving different comparison purposes across multiple phases. The same physical comparator unit performs different comparison tasks at different times by receiving different input pairs through the multiplexor routing system, thereby reducing the total quantity of comparators needed.
Solution Approach 2:
The system adds a time dimension to the comparison process. Instead of organizing comparators only in spatial stages, the invention introduces temporal phases where comparators are re-used across time, transforming the architecture from a purely spatial arrangement to a space-time multiplexed arrangement.
3Adaptability or versatility
If a complete sorting network is implemented, then full sorting capability is achieved, but the hardware complexity increases significantly
Solution Approach 1:
The system implements partial sorting capability sufficient for median filtering without achieving complete sorting. Since median filtering only requires finding the middle element(s), the comparison network is designed to provide just enough sorting capability to identify these elements, omitting redundant comparisons that would be necessary for complete sorting but unnecessary for the median operation.
Solution Approach 2:
The invention extracts only the essential comparison operations needed for median filtering from a complete sorting network. By removing unnecessary comparison stages and operations, the system retains the adaptability to find median values while significantly reducing hardware complexity.
4Area of stationary object
If the number of comparators is reduced, then the die area decreases, but the sorting speed may be affected
Solution Approach 1:
The sorting operation is divided into periodic phases that execute sequentially. While individual phases take time, the periodic re-use of comparators across phases maintains overall sorting throughput by keeping the comparison pipeline continuously active, preventing idle comparator periods and maintaining efficient utilization of the reduced hardware.
Solution Approach 2:
The system maintains continuous useful action by ensuring that comparators are actively performing comparisons in every phase without idle time. The scheduling circuit and multiplexors are designed to continuously route data through the comparison network, eliminating wasted cycles and maintaining sorting speed despite the reduced number of comparators.
Data Source
AI summary
Techniques are provided for sorting input data values using a sorting circuit. The sorting circuit includes a single stage of comparators coupled to a bank of registers. Multiplexors and a sequencer are used to route the comparator outputs back to the comparator inputs such that the comparators may be re-used over multiple sorting phases so as to order an input sequence of data values into a partially-sorted sequence or into a completely-sorted sequence that is monotonically increasing or decreasing. By re-using the comparators, the hardware required for such sorting is significantly reduced relative to conventional techniques. Also described are techniques for median filtering, which use a sorted sequence as output by the sorting circuit described herein.