SOS Wafer Opaque Pattern for Sensor Detection
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Solution Overview
Problem
The transparency of sapphire substrates in SOS wafers to light within the 670 to 940 nm wavelength range makes it difficult for transmission type sensors to detect the presence of SOS wafers during semiconductor chip manufacturing, leading to reduced production yield and efficiency.
Innovation Solution
A semiconductor wafer design with a silicon semiconductor layer on a sapphire substrate, featuring a chip forming area and a scribe line area with a pattern of opaque layers that improve detection without reducing the chip forming area, using poly-silicon films and conductive layers to create first, second, and third opaque pattern layers in a hound's tooth check pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the sapphire substrate is used as the insulation substrate in SOS wafer, then the electrical insulation performance is improved, but the transparency to light (670-940 nm) causes difficulty in detecting wafer presence
Solution Approach 1:
The patent applies local quality by making only specific regions of the wafer opaque (the scribe line area) while keeping the chip forming area transparent. This is achieved by forming an opaque pattern layer selectively in the scribe line region, which blocks light transmission locally to enable detection without affecting the overall wafer structure or chip quality.
Solution Approach 2:
The opaque pattern layer acts as an intermediary element that enables light interaction for detection purposes. By introducing this intermediate layer with specific optical properties (opacity), the system can detect wafer presence through light blocking while the sapphire substrate maintains its electrical insulation function.
2Measurement precision
If the outer contour portion is made amorphous to improve detection, then the recognition rate is improved, but the chip forming area is reduced
Solution Approach 1:
Instead of making the entire outer contour portion amorphous, the patent applies local quality by forming the opaque pattern layer only in the scribe line area. This selective approach ensures that the chip forming area remains fully intact and available for device fabrication, while only the necessary scribe line region is modified for detection purposes.
3Reliability
If additional processing steps are added to make the outer contour amorphous, then the detection reliability is improved, but the production time and cost increase
Solution Approach 1:
The patent merges the detection feature formation with the existing scribe line formation process. The opaque pattern layer is formed in the scribe line area using standard photolithography and deposition techniques that are already part of the manufacturing workflow, eliminating the need for separate amorphization processing steps.
Solution Approach 2:
The scribe line area serves multiple functions: it acts as the cutting line for separating chips, provides alignment references, and now also serves as the detection feature region. By making the opaque pattern layer part of the scribe line structure, the system achieves multi-functionality without adding separate processing steps.
4Measurement precision
If the outer contour portion is made amorphous, then the detection is improved, but the number of chips per wafer decreases
Solution Approach 1:
The patent applies local quality by restricting the opaque pattern layer formation to only the scribe line area, which is a narrow region between chips. This minimal modification approach preserves the maximum possible chip forming area, allowing the highest number of chips to be produced per wafer while still enabling reliable detection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the recognition rate of SOS wafers, improving production yield and efficiency by ensuring the wafer is detected accurately without additional processing steps and minimizing chip size reduction, thus preventing short circuits and easy chip washing.
Implementation Method 1
an opaque pattern layer formed in the scribe line area... A plurality of opaque pattern portions is arranged apart from each other in the opaque pattern layer
Data Source
AI summary
A semiconductor wafer includes an insulation substrate with transparency; a silicon semiconductor layer formed on the insulation substrate; a chip forming area defined on the silicon semiconductor layer; a scribe line area defined on the silicon semiconductor layer for dividing the chip forming area; and an opaque pattern layer formed in the scribe line area. A plurality of opaque pattern portions is arranged apart from each other in the opaque pattern layer.