System-on-Silicon Wafer Interconnect Layout for Multi-Die Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high performance and compact packaging of semiconductor devices due to limitations in miniaturization and integration density, particularly in wafer level integration and packaging processes.
Innovation Solution
The integration of a plurality of functional dies of different types in a single silicon wafer, combined with integrated redistribution and fan-out technology, to form a system-on-silicon wafer (SoSW) device with high performance in a compact and low-cost structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple functional dies are integrated on a single substrate using wafer level integration, then device size is reduced and integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the substrate into multiple regions, each dedicated to forming a specific type of functional die. This segmentation allows different die types to be manufactured simultaneously on the same substrate using type-specific process parameters, reducing manufacturing complexity while maintaining high integration density and compact device size.
Solution Approach 2:
The patent performs preliminary actions by forming all functional dies of different types on the substrate before singulation. This includes forming interconnect structures, conductive elements, and functional die structures in advance, allowing subsequent processing steps to be simplified and reducing overall manufacturing complexity.
2Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by using different process parameters for different regions of the substrate. Each region is optimized for its specific die type with appropriate feature sizes and process conditions, allowing high integration density overall while maintaining achievable manufacturing precision for each local area rather than requiring uniform ultra-fine precision across the entire substrate.
3Reliability
If functional dies of different types are formed on the same substrate, then system performance is improved through short communication channels, but process parameter optimization becomes more difficult
Solution Approach 1:
The patent implements parameter changes by adjusting process parameters according to the specific requirements of each die type and region. This allows optimal process conditions for each functional die type while maintaining the ability to form multiple die types on the same substrate, achieving both high system performance and manufacturability.
Data Source
AI summary
Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types.