1S1T1R SOT-MRAM Cell Area Reduction via Cross-Point Architecture
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Solution Overview
Problem
Conventional two-transistor one-resistor (2T1R) configuration for spin orbit torque magnetic tunnel junction random access memory (SOT-MRAM) devices occupies a large area, which is not suitable for the trend of miniaturization in semiconductor memory devices.
Innovation Solution
A memory device with a one-selector one-transistor one-resistor (1S1T1R) configuration is proposed, where a selector replaces the write transistor to reduce cell size, and a cross-point operating method is used to simplify memory array programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a two-transistor one-resistor (2T1R) configuration is used for SOT-MRAM devices, then the write operation can be controlled, but the cell area occupies a large space which is not suitable for miniaturization
Solution Approach 1:
The patent extracts the write transistor from the memory cell structure, separating the write control function from the storage function. The write transistor is moved to a shared structure outside the main cell, allowing the cell itself to be minimized to only the essential storage components (selector and resistor), thereby reducing cell area while preserving write operation control capability.
Solution Approach 2:
The patent implements a shared write transistor that serves multiple memory cells simultaneously. This single write transistor structure provides write control for multiple cells through word lines, eliminating the need for dedicated write transistors in each cell and achieving area reduction while maintaining operational control.
2Area of moving object
If a one-selector one-transistor one-resistor (1S1T1R) configuration is used, then the cell size is reduced, but the device complexity increases due to the cross-point operating method
Solution Approach 1:
The patent transitions from a planar memory array organization to a three-dimensional cross-point architecture where memory cells are arranged at intersections of bit lines and word lines. This dimensional change allows for more efficient space utilization and simplifies the write control mechanism by using selective line activation rather than individual cell control, thereby managing complexity while achieving compact cell size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 1S1T1R configuration reduces the cell size of the memory device, improving performance and increasing commercial competitiveness, while the cross-point method simplifies programming and enhances operational efficiency.
Implementation Method 1
spin orbit torque (SOT) layer, formed between the selector and the MTJ structure
Implementation Method 2
magnetic tunnel junction (MTJ) structure, disposed on the selector
Data Source
AI summary
Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.