SOT-MRAM Cell Layout for Tunnel Layer Reliability and Smaller Area
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Solution Overview
Problem
Conventional Spin-Transfer Torque (STT) MRAM cells face reliability issues due to programming currents passing through the tunnel layer, degrading it, whereas Spin Orbit Torque (SOT) MRAM cells improve reliability by avoiding current passage through the tunnel layer, but require additional process steps and larger cell sizes.
Innovation Solution
The formation of an SOT MRAM cell with an SOT layer beneath the MTJ stack, coupled to two transistors and a Reading Bit Line, reduces cell size and routing, improving speed and power efficiency by eliminating the need for additional vias and combining Word Lines for reading and writing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If STT-MRAM programming method is used, then the tunnel layer is directly programmed by current, but the tunnel layer degrades or damages due to current passage
Solution Approach 1:
The patent introduces a spin-orbit torque (SOT) layer as an intermediary between the current path and the tunnel layer. The programming current flows through the SOT layer instead of directly through the tunnel layer, which generates spin currents that act on the magnetic moments in the MTJ stack to switch the resistance state. This mediator approach protects the tunnel layer from direct current damage while still achieving programming functionality.
2Reliability
If SOT-MRAM structure is implemented, then reliability is improved by avoiding current through tunnel layer, but additional process steps and larger cell sizes are required
Solution Approach 1:
The patent combines the SOT layer formation with the existing MTJ stack formation process. The SOT layer is deposited as part of the blanket layer sequence along with the pinned layer, tunnel layer, and free layer, then all layers are patterned together in a single photolithography and etching step. This merging of processes eliminates the need for separate SOT layer fabrication steps, reducing overall process complexity despite the additional functional layer.
3Reliability
If SOT-MRAM structure is implemented, then reliability is improved by avoiding current through tunnel layer, but cell size increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking the SOT layer beneath the MTJ stack structure. Instead of expanding the SOT layer laterally, it is positioned in the vertical stacking sequence, allowing the same cell footprint to accommodate both the SOT functionality and the MTJ stack. This vertical integration minimizes the increase in cell area while maintaining the reliability benefits of the SOT architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the size and power consumption of SOT-MRAM devices, enhances operational speed, and simplifies the fabrication process by minimizing the number of process steps and routing, leading to improved memory density and reliability.
Implementation Method 1
Spin Orbit Torque (SOT) MRAM cells improve reliability by avoiding current passage through the tunnel layer
Implementation Method 2
Magneto-Resistive Random Access Memory (MRAM), which involves spin electronics that combines semiconductor technology and magnetic materials and devices. The spins of electrons, through their magnetic moments, rather than the charge of the electrons, are used to store bit values
Data Source
AI summary
A method includes depositing a first dielectric layer over a semiconductor substrate, depositing a first electrode layer over the first dielectric layer, etching the first electrode layer to form a first electrode and a second electrode laterally separated from the first electrode, depositing a Spin Orbit Torque (SOT) material on the first electrode and the second electrode, depositing Magnetic Tunnel Junction (MTJ) layers on the SOT material, depositing a second electrode layer on the MTJ layers, etching the SOT material to form a SOT layer extending from the first electrode to the second electrode, etching the MTJ layers to form an MTJ stack on the SOT layer, and etching the second electrode layer to form a top electrode on the MTJ stack.