SOT-MRAM Memory Subsystem for CNN AI Processing
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Solution Overview
Problem
Existing CNN-based ICs for AI are slow in computational speed and expensive, making them impractical for processing large amounts of imagery data, as they often rely on software solutions or hardware designed for general computation rather than being optimized for AI tasks.
Innovation Solution
A CNN-based digital IC with multiple processing units, each coupled to a memory subsystem containing MRAM cells with Spin-Orbit-Torque (SOT) based magnetic tunnel junction (MTJ) elements for efficient storage and processing of filter coefficients and imagery data, enabling processing-in-memory and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software solutions or general-purpose hardware are used for CNN processing, then adaptability is improved, but computational speed deteriorates
Solution Approach 1:
The patent replaces general-purpose software-based CNN processing with specialized hardware circuits that directly implement convolution operations. The CNN processing unit includes dedicated logic circuits for computing convolution results, eliminating the need for software execution and achieving significant speed improvement while maintaining adaptability through configurable architecture.
Solution Approach 2:
The patent changes the operational parameters by using magnetic memory cells with TMR effect to store weights and input data, enabling parallel read operations. The memory subsystem is configured to simultaneously provide multiple weights and input values to the processing unit, dramatically increasing computational throughput compared to sequential software processing.
2Adaptability or versatility
If general-purpose hardware is used for CNN processing, then adaptability is improved, but power consumption increases
Solution Approach 1:
The patent substitutes energy-intensive general-purpose processors with specialized CNN hardware that performs convolutions directly in circuit logic. The processing unit computes convolution results through dedicated arithmetic logic, eliminating the overhead of general-purpose instruction execution and reducing power consumption significantly.
Solution Approach 2:
The patent merges the memory storage function with the processing function by integrating magnetic memory cells directly with the CNN processing logic. This memory-processor integration eliminates data transfer between separate memory and processing units, reducing communication overhead and power consumption while maintaining architectural adaptability.
3Device complexity
If memory and processing units are separated, then functional clarity is improved, but read/write speed deteriorates
Solution Approach 1:
The patent implements a hierarchical memory structure where magnetic memory cells are nested within the CNN processing unit. The memory subsystem is integrated into the processing chip, with memory cells positioned in close proximity to the logic circuits, creating a nested architecture that maintains functional clarity while enabling fast data access.
Solution Approach 2:
The patent introduces magnetic memory cells with high TMR ratio as an intermediary between external memory and the processing unit. These memory cells act as a buffer that stores weights and input data locally, enabling rapid read operations without requiring continuous access to external memory, thus improving read/write speed while maintaining system modularity.
4Quantity of substance
If magnetic memory cells with high TMR ratio are used, then storage density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes the magnetic memory cell structure by adjusting the thickness and composition of the barrier layer and magnetic layers to achieve high TMR ratio. The free layer and pinned layer are engineered with specific magnetization directions and thicknesses, and the barrier layer is controlled to precise thickness ranges to maximize tunneling magnetoresistance while remaining compatible with standard semiconductor manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances computational speed and reduces power consumption by integrating memory and processing units on the same silicon, facilitating fast read/write operations and efficient storage of weights and imagery data, making it suitable for large-scale AI processing.
Implementation Method 1
Each MRAM cell contains a Spin-Orbit-Torque (SOT) based magnetic tunnel junction (MTJ) element
Data Source
AI summary
CNN (Cellular Neural Networks or Cellular Nonlinear Networks) based digital Integrated Circuit for artificial intelligence contains multiple CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem having first and second memories. The first memory contains magnetic random access memory (MRAM) cells for storing weights (e.g., filter coefficients) while the second memory is for storing input signals (e.g., imagery data). The first memory may store one-time-programming weights. The memory subsystem may contain a third memory that contains MRAM cells for storing one-time-programming data for security purpose. The second memory contains MRAM cells or static random access memory cells. Each MRAM cell contains a Spin-Orbit-Torque (SOT) based magnetic tunnel junction (MTJ) element.