SOT-MRAM Cell Layout With Self-Aligned MTJ Patterning
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Solution Overview
Problem
Conventional SOT-MRAM manufacturing processes face issues with alignment precision, leading to increased transistor size, higher power consumption, and metal redeposition on sidewalls, which degrades memory cell performance and results in variability between batches.
Innovation Solution
A self-aligned manufacturing process for SOT-MRAM cells, where electrically conductive lines are formed with depressions filled by a dielectric layer, ensuring precise alignment and minimizing metal redeposition, using a chemical mechanical polishing process to pattern the magnetic tunnel junction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional alignment operations are used in microfabrication processes, then manufacturing process simplicity is maintained, but alignment precision deteriorates leading to dimensional margins and variability between batches
Solution Approach 1:
The patent merges the alignment function into the etch mask structure itself. The etch mask includes alignment features that are inherently integrated with the pattern definition features, eliminating the need for separate alignment operations between different lithography steps. This integration of alignment and patterning functions into a single structure achieves high alignment precision without adding process complexity.
2Manufacturing precision
If the SOT layer width is increased to compensate for alignment imprecision, then alignment tolerance is improved, but device area increases limiting miniaturization
Solution Approach 1:
The patent performs alignment feature formation as a preliminary action during the etch mask fabrication step, before the actual SOT layer patterning. By pre-defining alignment references in the etch mask that are inherently aligned with the SOT layer boundaries, the subsequent patterning steps automatically inherit this alignment without requiring additional margin. This preliminary alignment action enables precise SOT layer definition with minimal width while maintaining alignment tolerance.
3Reliability
If etching processes are used to create gaps between connection layers, then electrical isolation is improved, but metal particle redeposition on sidewalls increases degrading performance
Solution Approach 1:
The patent extracts the gap formation function from the etching process and implements it through physical separation in the layer structure. Instead of creating gaps by removing material through etching (which causes metal particle redeposition), the design uses the natural physical separation between connection layers at different elevations, with insulating layers filling the space between them. This extraction of the gap formation function from the etching process eliminates the harmful metal particle redeposition while maintaining electrical isolation.
4Adaptability or versatility
If conventional multi-terminal configurations are used, then current routing flexibility is maintained, but device complexity and power consumption increase
Solution Approach 1:
The patent implements multi-functionality in the connection layer structure where the same connection layer serves multiple functions: it provides electrical connection to the SOT layer, acts as an etch stop layer for subsequent processing, and functions as an electrical isolation barrier. By making the connection layer universal and multi-functional, the design achieves current routing flexibility without requiring additional dedicated terminals or structures, thereby reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables precise alignment and reduced metal redeposition, allowing for scalable and consistent SOT-MRAM cells with improved performance and reduced power consumption.
Implementation Method 1
using a chemical mechanical polishing process to pattern the magnetic tunnel junction
Implementation Method 2
modification, or writing, of the state of the magnetic tunnel junction is carried out by circulating an electrical current in a spin-orbit interaction active layer, or SOT layer
Implementation Method 3
an electrically insulating tunnel layer that is thin enough to allow electrons to pass from one of the ferromagnetic layers to the second one by quantum tunneling
Implementation Method 4
The resistance of the MTJ to electrical current passage is governed by quantum mechanical physics and more specifically by Tunnel Magnetoresistance (TMR)
Data Source
Figure 1~4
Figure 5-1~5-2
Figure 5-3~5-4
AI summary
A SOT-MRAM (400) comprising a substrate dielectric layer (SubOx); a first and a second electrically conductive lines (ElA, ElB) formed in a same plane over the substrate dielectric layer (SubOx); a first dielectric layer (Diel1) over the substrate dielectric layer (SubOx) and interposed between the first and the second electrically conductive lines (ElA, ElB); a magnetic tunnel junction (MTJ) formed over the first dielectric layer (Diel1) and comprising a SOT layer (SOT) at a lowermost position of the magnetic tunnel junction (MTJ), the SOT layer (SOT) connecting the first electrically conductive layer (ElA) to the second electrically conductive layer (ElB), wherein top surfaces of the first and the second electrically conductive lines (ElA, ElB) present depressions at least partially filled with a second dielectric layer (Diel2).