SOT-MRAM Cell Layout With Shared Read-Write Transistors
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Solution Overview
Problem
The layout density of magnetic tunnel junctions in spin-orbit torque magnetic random access memory (SOT-MRAM) is limited due to the need for two transistors to control read and write operations, leading to a larger layout area and reduced integration density.
Innovation Solution
A magnetic storage structure with three transistors sharing two magnetic tunnel junctions, where one transistor performs the read operation and the other two transistors perform write operations, allowing for the storage and read of two-byte data, thereby reducing the number of transistors needed and increasing layout density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If two transistors are used to control read and write operations in each magnetic tunnel junction, then the read and write operations can be controlled, but the layout area increases and integration density decreases
Solution Approach 1:
The patent merges the control functions of multiple magnetic tunnel junctions into a shared transistor architecture. Specifically, one read transistor is shared by two magnetic tunnel junctions for read operations, and two write transistors are shared between them for write operations. This combining of control resources across multiple junctions reduces the total transistor count per junction from two to 0.5 on average, thereby reducing layout area while maintaining full control capability.
Solution Approach 2:
The patent implements multi-functionality by designing transistors that serve multiple purposes across different magnetic tunnel junctions. The read transistor functions as a shared control element for reading data from multiple junctions, and the write transistors serve dual purposes in setting the magnetic states of adjacent junctions. This universal usage of transistors across multiple junctions reduces the overall transistor requirement and increases integration density.
2Reliability
If more transistors are allocated per magnetic tunnel junction, then operational control is improved, but the number of transistors increases and layout density is reduced
Solution Approach 1:
The patent combines the operational control functions across multiple magnetic tunnel junctions by implementing shared read and write transistors. Instead of dedicating separate transistors to each junction, the control functionality is merged into shared elements that can selectively control multiple junctions through appropriate signal routing, thereby reducing transistor count while maintaining reliable operational control.
Solution Approach 2:
The patent employs dynamic control mechanisms where the shared transistors can be selectively activated to control different magnetic tunnel junctions based on operational requirements. The read transistor can be dynamically switched to control either of the two junctions for reading, and the write transistors can be dynamically activated to set specific junction states, providing flexible and reliable control with fewer static transistor requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the integration density of magnetic tunnel junctions and transistors, facilitating higher data storage capacity in a given space by optimizing the layout and reducing transistor count.
Implementation Method 1
With discovery of a spin-orbit torque effect, a spin-orbit torque magnetic random access memory (SOT-MRAM) is proposed. The SOT-MRAM generates a spin-transfer torque by means of spin flow induced by a charge flow on a basis of spin-orbit coupling to control a magnetic memory cell.
Data Source
AI summary
Embodiments provide a magnetic storage structure, a magnetic storage array structure, a control method, and a memory. The magnetic storage structure includes: two magnetic tunnel junctions, each of which includes a fixed layer and a free layer; spin-orbit coupling layers in one-to-one correspondence with the two magnetic tunnel junctions, where each of the spin-orbit coupling layers is positioned on a side of the free layer away from the fixed layer; a first transistor and a second transistor, where one of the spin-orbit coupling layers is electrically connected to a source terminal or a drain terminal of the first transistor, other one of the spin-orbit coupling layers is electrically connected to a source terminal or a drain terminal of the second transistor; and a third transistor, where a source terminal or a drain terminal of the third transistor is electrically connected to the fixed layers in the two magnetic tunnel junctions.