Output Enable Signal Control Circuit for SoundWire Power Reduction
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Solution Overview
Problem
The SoundWire protocol's power-intensive clock and logic circuitry for controlling data signals according to its timing constraints, which is inefficient in reducing power consumption.
Innovation Solution
A control circuit employing combinatorial logic to generate an output enable signal using a standard clock signal, a feedback clock signal, and a single data rate output stream, avoiding the need for fast clock circuitry by converting the signal to a double data rate stream to meet the protocol's timing constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fast clock circuitry is used to generate output enable signals meeting SoundWire timing constraints, then timing accuracy is improved, but power consumption increases
Solution Approach 1:
The patent changes the clock frequency parameter by using a slow clock signal instead of a fast clock signal to generate the output enable signal. This parameter change maintains timing accuracy for SoundWire protocol compliance while significantly reducing power consumption, as the slow clock operates at a lower frequency and consumes less energy.
Solution Approach 2:
The patent introduces a double data rate (DDR) conversion circuit as an intermediary component. This circuit converts the slow clock signal and single data rate output stream into a double data rate output stream, enabling the system to meet SoundWire timing constraints without requiring fast clock circuitry, thus resolving the contradiction between timing accuracy and power consumption.
2Use of energy by moving object
If double data rate conversion is implemented using slow clock signals, then power consumption is reduced, but circuit complexity increases
Solution Approach 1:
The patent segments the circuit into distinct functional blocks: a slow clock signal source, a double data rate conversion circuit, and an output enable circuit. This segmentation allows each block to perform its specific function efficiently, managing overall circuit complexity while achieving power reduction through the use of slow clock signals.
Solution Approach 2:
The patent implements a feedback mechanism where the double data rate conversion circuit receives the slow clock signal and single data rate output stream, processes them, and generates the double data rate output stream. The feedback loop ensures proper timing and synchronization, managing circuit complexity while maintaining power efficiency.
Data Source
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AI summary
Control circuits for generating output enable signals are disclosed. In one aspect, a control circuit is provided that employs combinatorial logic to generate an output enable signal that meets timing constraints using a standard clock signal, a feedback clock signal based on the standard clock signal, and a single data rate (SDR) data output stream. The control circuit includes a double data rate (DDR) conversion circuit configured to generate a DDR output stream based on a received SDR output stream. The control circuit includes an output enable circuit configured to receive the standard clock signal, feedback clock signal, and DDR output stream, and to generate the output enable signal that is asserted and de-asserted according to the defined timing constraints. The control circuit is configured to generate an accurately timed output enable signal without the need for a fast clock signal in addition to the standard clock signal.