Source Bias Circuit for Leakage Reduction in Memory Arrays
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Solution Overview
Problem
Existing memory systems face challenges in reducing leakage currents during standby mode, as applying reverse body bias reduces the effectiveness of source biasing, leading to diminished leakage reduction in memory arrays.
Innovation Solution
A source bias circuit with a diode-connected MOSFET is placed within the isolated well of the memory array, allowing it to track the well bias condition and maintain effective source biasing even when reverse body bias is applied, thereby reducing leakage currents without degrading the source bias voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If reverse body bias is applied to reduce leakage current, then leakage current is reduced, but the source bias voltage is reduced causing degradation of leakage reduction effectiveness
Solution Approach 1:
A diode-connected MOSFET is introduced as an intermediary element between the memory array and ground. This mediator tracks the well bias condition and provides a stable source bias voltage that compensates for the voltage reduction caused by reverse body bias, thereby maintaining effective leakage current suppression without degradation
Solution Approach 2:
The diode-connected MOSFET automatically tracks the well bias condition in real-time, creating a feedback mechanism that adjusts the source bias voltage to compensate for changes in leakage characteristics. This ensures continuous optimal performance of leakage reduction despite variations in operating conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that the source biasing effectiveness is retained during reverse body bias conditions, effectively reducing leakage currents in memory systems without compromising the source bias voltage, thus enhancing power conservation in battery-operated devices.
Implementation Method 1
applying a reverse body bias (RBB) to the well connection of the memory array transistors
Implementation Method 2
applying source biasing to the array devices (e.g. to the pulldown and pullup devices of a memory cell)
Data Source
AI summary
A memory system includes an isolated first well of a first polarity and an array of volatile memory cells. Each of the memory cells includes a first set of transistors in the isolated first well, and a second set of transistors. A source bias circuit is coupled to the array of volatile memory cells. At least a portion of the source bias circuit is in the isolated first well and coupled to source electrodes of the first set of transistors of each of the memory cells. A control circuit is configured to enable the source bias circuit.