Source Bias Transistors for PUF Bit Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing physically unclonable functions (PUFs) face challenges in achieving stable bit values due to manufacturing variations, temperature, and power supply fluctuations, leading to increased power consumption and area requirements on integrated circuits.
Innovation Solution
The implementation of an array of PUF cells with N-channel transistors connected to bit lines and source lines, utilizing always-on source bias transistors and margin transistors to enhance current differentials and reduce voltage swing, allowing for improved sensing and reduced power consumption, while identifying stable bits through enrollment processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SRAM-based PUF is implemented using 6-transistor cells, then PUF functionality is achieved, but area consumption increases
Solution Approach 1:
The PUF array is divided into multiple banks, each containing multiple PUF cells. This segmentation allows selective activation of only necessary cells for generating PUF bits, reducing the overall area required while maintaining sufficient stable bits for reliable PUF functionality.
Solution Approach 2:
Different regions of the PUF array can be optimized independently. The patent employs different transistor sizing strategies in different locations to maximize current differential and bit stability locally, thereby achieving reliable PUF bits with smaller cell sizes and reduced total area.
2Adaptability or versatility
If manufacturing variations are present, then device diversity is achieved, but PUF bit stability deteriorates
Solution Approach 1:
The patent systematically varies transistor dimensions (width and length) across different PUF cells to amplify the effects of manufacturing variations. By controlling the base transistor size and using sizing multipliers, the design ensures that small manufacturing variations are magnified into sufficient current differentials, improving both device uniqueness and bit stability.
Solution Approach 2:
Complementary PUF cells are designed with asymmetric transistor sizing to maximize the current differential effect. The n-type and p-type transistors in complementary cells are sized differently to enhance sensitivity to manufacturing variations, ensuring that each cell pair produces a stable, distinguishable output despite process variations.
3Measurement precision
If current differential is increased, then sensing accuracy is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by activating only the necessary number of PUF cells and banks required to generate sufficient stable bits, rather than operating all cells continuously. Transistors are sized to provide adequate current differential for sensing while avoiding excessive sizing that would unnecessarily increase power consumption.
Solution Approach 2:
Transistor width and length parameters are optimized to achieve the minimum necessary current differential for reliable sensing. The design uses calculated sizing multipliers to determine optimal transistor dimensions that balance sensing accuracy requirements with power consumption constraints, avoiding both undersizing and oversizing.
Data Source
AI summary
A physically unclonable function (PUF) includes an array of differential PUF bits arranged in rows and columns, wherein each differential bit is located at an intersection of a row and a column, and includes a first PUF cell coupled to a corresponding first bit line and first source line and a second PUF cell coupled to a corresponding second bit line and second source line. The PUF includes a source bias transistor coupled between each corresponding first source line and a first power supply terminal and between each corresponding second source line and the first power supply terminal, wherein a gate electrode of each of the source bias transistors is coupled to a second power supply terminal, and a corresponding set of margin transistors coupled in parallel with each source bias transistor, wherein a gate electrode of each margin transistor is coupled to receive a corresponding margin setting control signal.