Vertical Source Channel Contact for Void-Free Stack Filling
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Solution Overview
Problem
Existing gap-filling processes for high aspect ratio structures in semiconductor devices, such as vertical NAND, often result in voids and reliability issues due to incomplete filling and structural weaknesses.
Innovation Solution
A method involving the use of a multi-layer stack structure with alternating dielectric and sacrificial layers, combined with conductive layers having different wet etch rates, to form a source channel contact that fills high aspect ratio recesses without voids, ensuring stable barrier oxide formation and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gap-filling processes are used for high aspect ratio structures, then the filling process is simple, but voids and reliability issues occur due to incomplete filling
Solution Approach 1:
The fabrication process is divided into multiple stages: forming alternating dielectric and sacrificial layers, creating vertical recesses, filling with conductive material, and selective removal of sacrificial layers. This segmentation allows complete filling of high aspect ratio structures while maintaining reliability.
Solution Approach 2:
Dielectric and sacrificial layers are alternately stacked before forming the vertical recesses. This preliminary action creates a structured framework that guides the filling process and ensures complete material deposition without voids in high aspect ratio structures.
2Manufacturing precision
If conductive layers with different wet etch rates are used, then stable barrier oxide formation is achieved, but the manufacturing process becomes more complex
Solution Approach 1:
Different conductive layers are assigned different wet etch rates to achieve specific local functions. The first conductive layer forms a stable barrier oxide interface, while the second provides electrical connectivity. This local differentiation enables precise control of barrier oxide formation at critical interfaces.
Solution Approach 2:
The wet etch rate parameter is varied between different conductive layers to achieve selective removal and stable barrier oxide formation. By controlling this parameter, the process achieves precise interface formation and reliable electrical characteristics.
3Manufacturing precision
If multi-layer stack structures with alternating dielectric and sacrificial layers are formed, then high aspect ratio recesses are filled without voids, but the device structure becomes more complex
Solution Approach 1:
Sacrificial layers are introduced as intermediary elements that facilitate the gap-filling process. These layers are alternately stacked with dielectric layers, providing a framework that enables complete filling of high aspect ratio recesses. The sacrificial layers are subsequently removed to create the final structure.
Solution Approach 2:
The multi-layer stack structure embeds sacrificial layers within dielectric layers in a nested configuration. This nesting allows the filling material to be deposited completely without voids, as the sacrificial layers provide a structured pathway for material deposition in high aspect ratio geometries.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables reliable gap-filling of high aspect ratio structures in semiconductor devices, enhancing their structural integrity and reducing defects, thereby improving the reliability of the vertical semiconductor device.
Implementation Method 1
conductive layers having different wet etch rates
Data Source
AI summary
A vertical semiconductor device includes: a lower structure; a multi-layer stack structure including a source layer formed over the lower structure and gate electrodes formed over the source layer; a vertical structure penetrating the multi-layer stack structure and including a channel layer insulated from the source layer; a vertical source line spaced apart from the vertical structure to penetrate the multi-layer stack structure and contacting the source layer; and a horizontal source channel contact suitable for coupling the source layer and the channel layer and including a first conductive layer and a second conductive layer that include different dopants.