3D Memory Source Contact Layout for Stable Cell Stacking
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Solution Overview
Problem
The integration of 3D memory cell arrays in semiconductor memory devices compromises structural stability as the number of stacked memory cells increases.
Innovation Solution
A semiconductor memory device design featuring a gate stacked body, a source insulating structure, a source structure, a channel structure, and a memory layer, with a source contact structure that includes a first and second contact portion, enhancing structural stability through a specific manufacturing process involving sacrificial stacked body removal and replacement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked memory cells is increased to achieve large capacity, then the integration degree is improved, but the structural stability is compromised
Solution Approach 1:
The device is divided into multiple stacked memory cell layers, with each layer containing memory cells formed between word lines and bit lines. This segmentation allows the memory capacity to be increased by adding more layers while maintaining the structural integrity of each individual layer, thereby resolving the contradiction between high capacity and structural stability.
Solution Approach 2:
The patent transitions from two-dimensional planar memory architecture to three-dimensional stacked architecture. By stacking multiple memory cell layers vertically, the memory capacity is significantly increased without expanding the planar area, while each layer maintains its structural stability through proper design of word lines, bit lines, and contact structures.
2Productivity
If the integration degree is improved by stacking more memory cells, then the memory capacity increases, but the device complexity increases
Solution Approach 1:
The complex three-dimensional structure is segmented into repeating modular units, where each memory cell layer follows a standardized configuration of word lines, bit lines, and contact structures. This modularity simplifies the manufacturing process and reduces overall device complexity while still achieving high memory capacity through vertical stacking.
Solution Approach 2:
Multiple memory cell layers are nested vertically, with each layer containing smaller-scale structures (word lines, bit lines, contacts) that are systematically arranged. This nested architecture allows the complex functionality to be achieved through hierarchical organization, where simpler repeating units combine to form the complete high-capacity memory device.
3Productivity
If the number of stacked memory cells is increased, then the memory capacity increases, but the manufacturing precision requirements increase
Solution Approach 1:
The manufacturing process is divided into sequential steps for forming each memory cell layer, with standardized procedures for creating word lines, bit lines, and contact structures. This segmentation allows for systematic control of alignment precision at each stage, ensuring that even as the number of stacked layers increases, the manufacturing precision requirements remain manageable through repeated application of proven fabrication techniques.
Data Source
AI summary
Provided herein is a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a gate stacked body, a first semiconductor layer over the gate stacked body, a source insulating structure between the first semiconductor layer and the gate stacked body, a contact source layer disposed between the source insulating structure and the gate stacked body, a channel structure penetrating the gate stacked body and contacting the contact source layer, a memory layer between the gate stacked body and the channel structure, and a source contact structure coupled to the contact source layer and extending to penetrate the source insulating structure and the first semiconductor layer.