3D Source Contact Layout for Low-Capacitance Power Rail ICs
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling transistor devices due to increased contact resistance and parasitic capacitance as feature sizes decrease, leading to complex manufacturing processes and reduced operating speeds.
Innovation Solution
The introduction of structural features for source contacts in integrated circuit devices that reduce parasitic capacitance and contact resistance, allowing for increased operating speeds while relaxing critical dimension and process window requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is reduced to increase integration density, then functional density is improved, but contact resistance and parasitic capacitance increase
Solution Approach 1:
The source contact structure transitions from a planar configuration to a three-dimensional structure with a vertical portion extending along the sidewall of the source feature. This dimensional change allows the contact to reach the power supply line at a different vertical level, reducing parasitic capacitance while maintaining electrical connectivity despite reduced feature sizes
Solution Approach 2:
The source contact is divided into two distinct portions: a lateral portion that contacts the source feature and a vertical portion that extends along the sidewall to contact the power supply line. This segmentation allows each portion to be optimized independently, with the vertical portion specifically designed to minimize parasitic capacitance with adjacent drain contacts
2Quantity of substance
If feature size is reduced to increase integration density, then functional density is improved, but parasitic capacitance increases
Solution Approach 1:
By extending the source contact vertically along the sidewall of the source feature, the contact reaches the power supply line at a higher vertical position. This places the source contact further away from adjacent drain contacts in the vertical dimension, thereby reducing parasitic capacitance between source and drain regions
Solution Approach 2:
The vertical portion of the source contact acts as an intermediary structure that bridges the lateral portion (contacting source feature) and the power supply line. This intermediate vertical extension allows the contact to achieve electrical connectivity while minimizing capacitive coupling with adjacent structures
3Ease of manufacture
If conventional source contact structures are used, then manufacturing process is simple, but operating speed is reduced due to high parasitic capacitance and contact resistance
Solution Approach 1:
The source contact structure is designed in advance with a specific three-dimensional configuration including the vertical portion along the sidewall. This preliminary structural design ensures that parasitic capacitance is minimized before device operation, enabling high-speed performance without requiring complex manufacturing steps
Solution Approach 2:
The source contact geometry is changed from a conventional planar shape to a three-dimensional structure with controlled dimensions. The vertical portion has specific length and positioning parameters that are optimized to reduce parasitic capacitance, and these geometric parameters can be adjusted during device design to achieve desired performance
4Quantity of substance
If feature size is reduced, then integration density is improved, but critical dimension and process window requirements become more constrained
Solution Approach 1:
By segmenting the source contact into lateral and vertical portions, the manufacturing process can focus on forming each portion with appropriate precision. The vertical portion can be formed using standard lithography and etching processes with relaxed critical dimension requirements compared to forming the entire contact structure in a single step
Data Source
AI summary
A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.