Vertical Semiconductor Source Contact Sealing for Void-Free Gapfill
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Solution Overview
Problem
The fabrication of vertical semiconductor devices faces challenges in achieving reliable gapfill processes for high aspect ratio structures, particularly in forming sealing spacers with different etch resistance than dielectric layers, which affects the integrity and reliability of the device.
Innovation Solution
A method involving the formation of a carbon-containing spacer with high wet-etch resistance, alternately stacked with dielectric layers and gate electrodes, to seal the vertical contact recess and prevent Grown Bad Blocks (GBB) defects, while ensuring the sealing spacer remains intact during cleaning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sealing spacer is formed to seal the vertical contact recess, then the integrity and reliability of the device is improved, but the manufacturing complexity increases due to the requirement of different etch resistance between sealing spacer and dielectric layers
Solution Approach 1:
The patent applies local quality by forming a sealing spacer with different etch resistance properties than the surrounding dielectric layers. The sealing spacer is specifically engineered to have high wet-etch resistance while other dielectric layers have different etch characteristics, allowing selective removal of sacrificial layers and precise formation of the sealing structure in high aspect ratio contact recesses.
Solution Approach 2:
The patent utilizes parameter changes by varying the etch resistance properties of different layers through material selection and deposition conditions. The sealing spacer is formed with controlled thickness and material composition to achieve the required etch resistance differential, enabling the gapfill process to proceed with proper sealing while managing manufacturing complexity.
2Stability of the object's composition
If the sealing spacer is made with high wet-etch resistance, then the spacer remains intact during cleaning processes, but the difficulty of forming the spacer with different etch resistance than dielectric layers increases
Solution Approach 1:
The patent applies preliminary action by forming the sealing spacer with high wet-etch resistance before the cleaning processes occur. This ensures the spacer is already in place and will remain intact during subsequent cleaning steps, preventing defects while maintaining manufacturing feasibility through proper process sequencing.
Solution Approach 2:
The patent employs composite materials by combining different dielectric layers with distinct etch resistance properties. The sealing spacer is formed as a composite structure with materials selected to provide high wet-etch resistance, creating a multi-layer system where each layer serves a specific function in the fabrication process.
3Shape
If the gapfill process is performed to form high aspect ratio structures, then the vertical semiconductor device structure is achieved, but the reliability is compromised due to difficulty in forming sealing spacers with different etch resistance
Solution Approach 1:
The patent applies segmentation by dividing the dielectric structure into multiple layers with different etch resistance properties. The sealing spacer is segmented as a distinct layer with high wet-etch resistance, while other dielectric layers have different etch characteristics. This segmentation enables the formation of high aspect ratio structures through gapfill processes while maintaining reliability through proper sealing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the reliability of vertical semiconductor devices by reducing chip size, preventing voids in the source contact plug, and improving electrical characteristics by maintaining the thickness and integrity of the sealing spacer despite high voltage applications.
Implementation Method 1
forming a carbon-containing spacer with high wet-etch resistance
Data Source
AI summary
A method for fabricating a semiconductor device includes: forming a first multi-layer stack including liner layers and a source sacrificial layer over a lower structure; forming a second multi-layer stack including dielectric layers and sacrificial layers over the first multi-layer stack; forming a vertical contact recess extending through the second multi-layer stack and the source sacrificial layer; replacing the source sacrificial layer with a source contact layer; forming a carbon-containing spacer on sidewall of the vertical contact recess; replacing the sacrificial layers with conductive layers; and forming a source contact plug in the vertical contact recess.