Source Core Interrupt Steering via Request-Directed Interrupts
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Solution Overview
Problem
Storage input/output (I/O) throughput is bottlenecked by interrupt processing in multi-core processor systems due to inefficient interrupt distribution, leading to core saturation and increased latency as the number of processor cores increases.
Innovation Solution
The implementation of Request-Directed Interrupts (RDIs) using Core-IDs, which embed an address offset or logical handle in I/O requests to direct interrupts back to the source core, allowing for efficient load-balancing and context cache hits, thereby reducing inter-processor interrupt overhead and promoting processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If interrupts are directed to a specific core using fixed-mode policy, then interrupt processing is simplified, but core saturation occurs and processing efficiency deteriorates
Solution Approach 1:
The patent implements dynamic interrupt steering that adapts interrupt distribution based on real-time core utilization metrics. The system transitions from static fixed-mode policy to dynamic load-based distribution, where the interrupt target core is selected based on current system state, preventing core saturation while maintaining processing efficiency
Solution Approach 2:
The system changes the parameter of interrupt target selection from a fixed core identifier to a dynamically determined core based on utilization metrics. By monitoring core utilization parameters and adjusting interrupt steering decisions accordingly, the system optimizes both processing complexity and efficiency
2Productivity
If interrupts are spread randomly or round-robin to multiple cores, then core saturation is reduced, but context mismatch increases and latency worsens
Solution Approach 1:
The patent implements a feedback mechanism that monitors core utilization metrics and uses this information to make intelligent interrupt steering decisions. The system continuously gathers feedback on core load states and adjusts interrupt distribution accordingly, ensuring interrupts are directed to appropriate cores based on real-time conditions rather than random or round-robin selection
Solution Approach 2:
The system performs preliminary assessment of core utilization states before directing interrupts. By evaluating core load metrics in advance and pre-determining the most appropriate target core based on current system state, the system avoids context mismatch and reduces latency while maintaining balanced core utilization
3Power
If the number of processor cores increases, then processing capacity increases, but interrupt distribution complexity and latency increase
Solution Approach 1:
The patent implements a dynamic interrupt steering mechanism that scales efficiently with the number of cores. The system adapts to any configuration of processor cores by continuously monitoring utilization metrics across all cores and dynamically selecting appropriate target cores, making the interrupt distribution mechanism scalable without increasing latency
Data Source
AI summary
An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein.