Source-Coupled Stacked Transistor Package for Thermal Reliability
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Solution Overview
Problem
Packages with power semiconductor chips face reliability and performance issues due to significant heat generation during operation, which affects their thermal reliability and efficiency.
Innovation Solution
A package design featuring a vertical stack of two source-coupled transistor chips with mutual source coupling, which reduces heat generation and power loss, and allows for efficient heat removal through double-sided cooling and a compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power semiconductor chips are used to increase power output, then power capability is improved, but heat generation increases causing reliability deterioration
Solution Approach 1:
The invention divides the heat management function into multiple independent heat sinks positioned at different locations (top surface and side surfaces) of the package. This segmentation allows heat to be dissipated from multiple pathways simultaneously, reducing the thermal load on any single heat sink and improving overall thermal reliability while maintaining high power output capability.
2Power
If multiple transistor chips are stacked to increase power capability, then power output is improved, but device complexity increases
Solution Approach 1:
The invention merges multiple heat dissipation functions into a single integrated package structure. Multiple transistor chips are stacked vertically on a common substrate, with heat sinks integrated at the top and side surfaces. This merging approach achieves high power output through chip stacking while the unified package structure manages the complexity of heat dissipation, interconnections, and mechanical support in an integrated manner.
3Reliability
If heat dissipation structures are added to improve thermal management, then thermal reliability is improved, but device complexity increases
Solution Approach 1:
The package substrate serves multiple functions simultaneously: it provides mechanical support for the stacked transistor chips, establishes electrical interconnections between chips, and acts as a thermal management platform with integrated heat sinks at the top and side surfaces. This multi-functionality improves thermal reliability without proportionally increasing device complexity, as the same structural elements perform multiple roles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stacked source-coupled transistor chip package achieves low thermal resistance, high current gain, and enhanced heat spreading, improving thermal reliability and performance while maintaining a compact footprint suitable for power semiconductor applications.
Implementation Method 1
simulations have shown that stacked transistor chips with mutual source coupling are characterized by a low heat generation and in particular show a significantly lower power loss than a comparable design with drain coupling
Implementation Method 2
stacked transistor chips with mutual source coupling are characterized by a low heat generation and in particular show a significantly lower power loss
Data Source
AI summary
A package and method of manufacturing a package is disclosed. In one example, a package which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area. The first source pad and the second source pad are coupled at the interface area.